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| REJ09B0430-0100 16 H8/38704 Group, H8/38702S Group Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Super Low Power Series H8/38704 Group H8/38702S Group H8/38704 H8/38703 H8/38702 H8/38702S H8/38701S H8/38700S All information contained in this material, including products and product specifications at the time of publication of this material, is subject to change by Renesas Technology Corp. without notice. Please review the latest information published by Renesas Technology Corp. through various means, including the Renesas Technology Corp. website (http://www.renesas.com). Rev.1.00 Revision Date: Dec. 13, 2007 Rev. 1.00 Dec. 13, 2007 Page ii of xviii Notes regarding these materials 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries. Rev. 1.00 Dec. 13, 2007 Page iii of xviii General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1. Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual. The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. Unused pins should be handled as described under Handling of Unused Pins in the manual. 2. Processing at Power-on The state of the product is undefined at the moment when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited. The reserved addresses are provided for the possible future expansion of functions. Do not access these addresses; the correct operation of LSI is not guaranteed if they are accessed. 4. Clock Signals After applying a reset, only release the reset line after the operating clock signal has become stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized. When the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. Differences between Products Before changing from one product to another, i.e. to one with a different type number, confirm that the change will not lead to problems. The characteristics of MPU/MCU in the same group but having different type numbers may differ because of the differences in internal memory capacity and layout pattern. When changing to products of different type numbers, implement a system-evaluation test for each of the products. Rev. 1.00 Dec. 13, 2007 Page iv of xviii How to Use This Manual 1. Objective and Target Users This manual was written to explain the hardware functions and electrical characteristics of this LSI to the target users, i.e. those who will be using this LSI in the design of application systems. Target users are expected to understand the fundamentals of electrical circuits, logic circuits, and microcomputers. This manual is organized in the following items: an overview of the product, descriptions of the CPU, system control functions, and peripheral functions, electrical characteristics of the device, and usage notes. When designing an application system that includes this LSI, take all points to note into account. Points to note are given in their contexts and at the final part of each section, and in the section giving usage notes. The list of revisions is a summary of major points of revision or addition for earlier versions. It does not cover all revised items. For details on the revised points, see the actual locations in the manual. The following documents have been prepared for the H8/38704 Group and the H8/38702S Group. Before using any of the documents, please visit our web site to verify that you have the most up-to-date available version of the document. Document Type Data Sheet Hardware Manual Contents Document Title Document No. This manual Overview of hardware and electrical characteristics Hardware specifications (pin assignments, memory maps, peripheral specifications, electrical characteristics, and timing charts) and descriptions of operation Detailed descriptions of the CPU and instruction set Examples of applications and sample programs Preliminary report on the specifications of a product, document, etc. H8/38704, H8/38702S Group Hardware Manual Software Manual Application Note Renesas Technical Update H8/300H Series Software Manual REJ09B0213 The latest versions are available from our web site. Rev. 1.00 Dec. 13, 2007 Page v of xviii 2. Description of Numbers and Symbols Aspects of the notations for register names, bit names, numbers, and symbolic names in this manual are explained below. (1) Overall notation In descriptions involving the names of bits and bit fields within this manual, the modules and registers to which the bits belong may be clarified by giving the names in the forms "module name"."register name"."bit name" or "register name"."bit name". (2) Register notation The style "register name"_"instance number" is used in cases where there is more than one instance of the same function or similar functions. [Example] CMCSR_0: Indicates the CMCSR register for the compare-match timer of channel 0. (3) Number notation Binary numbers are given as B'nnnn (B' may be omitted if the number is obviously binary), hexadecimal numbers are given as H'nnnn or 0xnnnn, and decimal numbers are given as nnnn. [Examples] Binary: B'11 or 11 Hexadecimal: H'EFA0 or 0xEFA0 Decimal: 1234 (4) Notation for active-low An overbar on the name indicates that a signal or pin is active-low. [Example] WDTOVF (4) (2) 14.2.2 Compare Match Control/Status Register_0, _1 (CMCSR_0, CMCSR_1) CMCSR indicates compare match generation, enables or disables interrupts, and selects the counter input clock. Generation of a WDTOVF signal or interrupt initializes the TCNT value to 0. 14.3 Operation 14.3.1 Interval Count Operation When an internal clock is selected with the CKS1 and CKS0 bits in CMCSR and the STR bit in CMSTR is set to 1, CMCNT starts incrementing using the selected clock. When the values in CMCNT and the compare match constant register (CMCOR) match, CMCNT is cleared to H'0000 and the CMF flag in CMCSR is set to 1. When the CKS1 and CKS0 bits are set to B'01 at this time, a f/4 clock is selected. Rev. 0.50, 10/04, page 416 of 914 (3) Note: The bit names and sentences in the above figure are examples and have nothing to do with the contents of this manual. Rev. 1.00 Dec. 13, 2007 Page vi of xviii 3. Description of Registers Each register description includes a bit chart, illustrating the arrangement of bits, and a table of bits, describing the meanings of the bit settings. The standard format and notation for bit charts and tables are described below. [Table of Bits] (1) Bit 15 14 13 to 11 10 9 (2) Bit Name - - ASID2 to ASID0 - - - (3) (4) Description Reserved These bits are always read as 0. Address Identifier These bits enable or disable the pin function. Reserved This bit is always read as 0. Reserved This bit is always read as 1. (5) Initial Value R/W 0 0 All 0 0 1 0 R R R/W R R Note: The bit names and sentences in the above figure are examples, and have nothing to do with the contents of this manual. (1) Bit Indicates the bit number or numbers. In the case of a 32-bit register, the bits are arranged in order from 31 to 0. In the case of a 16-bit register, the bits are arranged in order from 15 to 0. (2) Bit name Indicates the name of the bit or bit field. When the number of bits has to be clearly indicated in the field, appropriate notation is included (e.g., ASID[3:0]). A reserved bit is indicated by "-". Certain kinds of bits, such as those of timer counters, are not assigned bit names. In such cases, the entry under Bit Name is blank. (3) Initial value Indicates the value of each bit immediately after a power-on reset, i.e., the initial value. 0: The initial value is 0 1: The initial value is 1 -: The initial value is undefined (4) R/W For each bit and bit field, this entry indicates whether the bit or field is readable or writable, or both writing to and reading from the bit or field are impossible. The notation is as follows: R/W: The bit or field is readable and writable. R/(W): The bit or field is readable and writable. However, writing is only performed to flag clearing. R: The bit or field is readable. "R" is indicated for all reserved bits. When writing to the register, write the value under Initial Value in the bit chart to reserved bits or fields. W: The bit or field is writable. (5) Description Describes the function of the bit or field and specifies the values for writing. Rev. 1.00 Dec. 13, 2007 Page vii of xviii 4. Description of Abbreviations The abbreviations used in this manual are listed below. * Abbreviations used in this manual Description Asynchronous communication interface adapter Bits per second Cyclic redundancy check Direct memory access Direct memory access controller Global System for Mobile Communications High impedance Inter Equipment Bus (IEBus is a trademark of NEC Electronics Corporation.) Input/output Infrared Data Association Least significant bit Most significant bit No connection Phase-locked loop Pulse width modulation Special function register Subscriber Identity Module Universal asynchronous receiver/transmitter Voltage-controlled oscillator Abbreviation ACIA bps CRC DMA DMAC GSM Hi-Z IEBus I/O IrDA LSB MSB NC PLL PWM SFR SIM UART VCO Rev. 1.00 Dec. 13, 2007 Page viii of xviii 5. List of Product Specifications Below is a table listing the product specifications for each group. H8/38704 Group Item Memory ROM RAM Operating 4.5 to 5.5 V voltage 2.7 to 5.5 V and operating 1.8 to 5.5 V frequency 2.7 to 3.6 V 1.8 to 3.6 V I/O ports Input Output I/O Timers Clock (timer A) Compare (timer F) AEC WDT WDT (discrete) UART/Clock frequency A-D (resolution x input channels) External interrupt (internal wakeup) Package SCI Flash Memory 16 k, 32 kbytes 1 kbyte -- -- -- 10 MHz 4 MHz (2.2 V or more) 9 6 39 1 1 1 1 -- 1 ch 10 bit x 4 ch 11(8) Mask ROM 16 k, 24 k, 32 kbytes 1 kbyte 16 MHz 16 MHz -- -- -- 9 5 39 1 1 1 1 -- 1 ch 10 bit x 4 ch 11(8) H8/38702S Group Mask ROM 8 k, 12 k, 16 kbytes 512 bytes -- -- -- 10 MHz 4 MHz 9 6 39 1 1 1 1 -- 1 ch 10 bit x 4 ch 11(8) Operating temperature FP-64A FP-64A FP-64A FP-64E FP-64E FP-64K TNP-64B TNP-64B -- Standard specifications: -20 to 75C, WTR: -40 to 85C All trademarks and registered trademarks are the property of their respective owners. Rev. 1.00 Dec. 13, 2007 Page ix of xviii Contents Section 1 Overview ............................................................................................... 1 1.1 Features................................................................................................................................. 1 1.1.1 Application ........................................................................................................... 1 1.1.2 Overview of Specifications................................................................................... 2 List of Products..................................................................................................................... 5 Block Diagram...................................................................................................................... 7 Pin Assignment..................................................................................................................... 8 Pin Functions ........................................................................................................................ 9 1.2 1.3 1.4 1.5 Section 2 CPU ..................................................................................................... 13 2.1 2.2 Address Space and Memory Map ....................................................................................... 15 Register Configuration........................................................................................................ 21 2.2.1 General Registers................................................................................................ 22 2.2.2 Program Counter (PC) ........................................................................................ 23 2.2.3 Condition-Code Register (CCR)......................................................................... 23 Data Formats....................................................................................................................... 25 2.3.1 General Register Data Formats........................................................................... 25 2.3.2 Memory Data Formats ........................................................................................ 27 Instruction Set..................................................................................................................... 28 2.4.1 Table of Instructions Classified by Function ...................................................... 28 2.4.2 Basic Instruction Formats ................................................................................... 38 Addressing Modes and Effective Address Calculation....................................................... 39 2.5.1 Addressing Modes .............................................................................................. 39 2.5.2 Effective Address Calculation ............................................................................ 43 Basic Bus Cycle.................................................................................................................. 45 2.6.1 Access to On-Chip Memory (RAM, ROM)........................................................ 45 2.6.2 On-Chip Peripheral Modules .............................................................................. 46 CPU States .......................................................................................................................... 47 Usage Notes ........................................................................................................................ 48 2.8.1 Notes on Data Access to Empty Areas ............................................................... 48 2.8.2 EEPMOV Instruction.......................................................................................... 48 2.8.3 Bit-Manipulation Instruction .............................................................................. 49 2.3 2.4 2.5 2.6 2.7 2.8 Section 3 Exception Handling ............................................................................. 55 3.1 3.2 Exception Sources and Vector Address .............................................................................. 58 Register Descriptions.......................................................................................................... 59 Rev. 1.00 Dec. 13, 2007 Page x of xviii 3.3 3.4 3.5 3.2.1 Interrupt Edge Select Register (IEGR) ............................................................... 59 3.2.2 Interrupt Enable Register 1 (IENR1) .................................................................. 60 3.2.3 Interrupt Enable Register 2 (IENR2) .................................................................. 61 3.2.4 Interrupt Request Register 1 (IRR1) ................................................................... 62 3.2.5 Interrupt Request Register 2 (IRR2) ................................................................... 63 3.2.6 Wakeup Interrupt Request Register (IWPR)....................................................... 64 3.2.7 Wakeup Edge Select Register (WEGR).............................................................. 65 Reset Exception Handling................................................................................................... 65 Interrupt Exception Handling ............................................................................................. 66 3.4.1 External Interrupts .............................................................................................. 66 3.4.2 Internal Interrupts ............................................................................................... 67 3.4.3 Interrupt Handling Sequence .............................................................................. 68 3.4.4 Interrupt Response Time..................................................................................... 69 Usage Notes ........................................................................................................................ 71 3.5.1 Interrupts after Reset........................................................................................... 71 3.5.2 Notes on Stack Area Use .................................................................................... 71 3.5.3 Interrupt Request Flag Clearing Method............................................................. 71 3.5.4 Notes on Rewriting Port Mode Registers............................................................ 72 Section 4 Clock Pulse Generators........................................................................75 4.1 4.2 Features............................................................................................................................... 75 System Clock Generator ..................................................................................................... 76 4.2.1 Connecting Crystal Resonator ............................................................................ 76 4.2.2 Connecting Ceramic Resonator .......................................................................... 77 4.2.3 External Clock Input Method.............................................................................. 77 Subclock Generator............................................................................................................. 78 4.3.1 Connecting 32.768-kHz/38.4-kHz Crystal Resonator......................................... 78 4.3.2 Pin Connection when Not Using Subclock......................................................... 79 4.3.3 External Clock Input ........................................................................................... 80 Prescalers ............................................................................................................................ 80 4.4.1 Prescaler S .......................................................................................................... 80 4.4.2 Prescaler W ......................................................................................................... 80 Usage Notes ........................................................................................................................ 81 4.5.1 Note on Resonators............................................................................................. 81 4.5.2 Notes on Board Design ....................................................................................... 82 4.5.3 Definition of Oscillation Stabilization Standby Time......................................... 83 4.5.4 Notes on Use of Resonator ................................................................................. 85 4.3 4.4 4.5 Rev. 1.00 Dec. 13, 2007 Page xi of xviii Section 5 Power-Down Modes............................................................................ 87 5.1 Register Descriptions.......................................................................................................... 88 5.1.1 System Control Register 1 (SYSCR1) ................................................................ 88 5.1.2 System Control Register 2 (SYSCR2) ................................................................ 90 5.1.3 Clock Halt Registers 1 and 2 (CKSTPR1 and CKSTPR2) ................................. 91 Mode Transitions and States of LSI.................................................................................... 92 5.2.1 Sleep Mode ......................................................................................................... 98 5.2.2 Standby Mode..................................................................................................... 99 5.2.3 Watch Mode........................................................................................................ 99 5.2.4 Subsleep Mode.................................................................................................. 100 5.2.5 Subactive Mode ................................................................................................ 100 5.2.6 Active (Medium-Speed) Mode ......................................................................... 101 Direct Transition............................................................................................................... 102 5.3.1 Direct Transition from Active (High-Speed) Mode to Active (Medium-Speed) Mode ..................................................................................... 103 5.3.2 Direct Transition from Active (Medium-Speed) Mode to Active (High-Speed) Mode .......................................................................................... 104 5.3.3 Direct Transition from Subactive Mode to Active (High-Speed) Mode........... 104 5.3.4 Direct Transition from Subactive Mode to Active (Medium-Speed) Mode ..... 105 5.3.5 Notes on External Input Signal Changes before/after Direct Transition........... 105 Module Standby Function................................................................................................. 106 Usage Notes ...................................................................................................................... 106 5.5.1 Standby Mode Transition and Pin States .......................................................... 106 5.5.2 Notes on External Input Signal Changes before/after Standby Mode............... 107 5.2 5.3 5.4 5.5 Section 6 ROM .................................................................................................. 109 6.1 6.2 Block Diagram.................................................................................................................. 109 Overview of Flash Memory.............................................................................................. 110 6.2.1 Features............................................................................................................. 110 6.2.2 Block Diagram.................................................................................................. 111 6.2.3 Block Configuration ......................................................................................... 112 Register Descriptions........................................................................................................ 113 6.3.1 Flash Memory Control Register 1 (FLMCR1).................................................. 114 6.3.2 Flash Memory Control Register 2 (FLMCR2).................................................. 115 6.3.3 Erase Block Register (EBR) ............................................................................. 115 6.3.4 Flash Memory Power Control Register (FLPWCR)......................................... 116 6.3.5 Flash Memory Enable Register (FENR)........................................................... 116 On-Board Programming Modes........................................................................................ 117 6.4.1 Boot Mode ........................................................................................................ 117 6.3 6.4 Rev. 1.00 Dec. 13, 2007 Page xii of xviii 6.5 6.6 6.7 6.8 6.4.2 Programming/Erasing in User Program Mode.................................................. 120 Flash Memory Programming/Erasing............................................................................... 121 6.5.1 Program/Program-Verify .................................................................................. 122 6.5.2 Erase/Erase-Verify............................................................................................ 125 6.5.3 Interrupt Handling when Programming/Erasing Flash Memory....................... 125 Program/Erase Protection ................................................................................................. 127 6.6.1 Hardware Protection ......................................................................................... 127 6.6.2 Software Protection........................................................................................... 127 6.6.3 Error Protection................................................................................................. 127 Programmer Mode ............................................................................................................ 128 6.7.1 Socket Adapter.................................................................................................. 128 6.7.2 Programmer Mode Commands ......................................................................... 128 6.7.3 Memory Read Mode ......................................................................................... 131 6.7.4 Auto-Program Mode ......................................................................................... 134 6.7.5 Auto-Erase Mode.............................................................................................. 136 6.7.6 Status Read Mode ............................................................................................. 137 6.7.7 Status Polling .................................................................................................... 139 6.7.8 Programmer Mode Transition Time ................................................................. 140 6.7.9 Notes on Memory Programming....................................................................... 140 Power-Down States for Flash Memory............................................................................. 141 Section 7 RAM ..................................................................................................143 7.1 Block Diagram.................................................................................................................. 144 Section 8 I/O Ports .............................................................................................145 8.1 Port 3................................................................................................................................. 147 8.1.1 Port Data Register 3 (PDR3)............................................................................. 148 8.1.2 Port Control Register 3 (PCR3) ........................................................................ 148 8.1.3 Port Pull-Up Control Register 3 (PUCR3)........................................................ 149 8.1.4 Port Mode Register 3 (PMR3) .......................................................................... 150 8.1.5 Port Mode Register 2 (PMR2) .......................................................................... 151 8.1.6 Pin Functions .................................................................................................... 152 8.1.7 Input Pull-Up MOS........................................................................................... 153 Port 4................................................................................................................................. 154 8.2.1 Port Data Register 4 (PDR4)............................................................................. 154 8.2.2 Port Control Register 4 (PCR4) ........................................................................ 155 8.2.3 Serial Port Control Register (SPCR)................................................................. 155 8.2.4 Pin Functions .................................................................................................... 157 Port 5................................................................................................................................. 158 8.3.1 Port Data Register 5 (PDR5)............................................................................. 159 Rev. 1.00 Dec. 13, 2007 Page xiii of xviii 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.3.2 Port Control Register 5 (PCR5) ........................................................................ 159 8.3.3 Port Pull-Up Control Register 5 (PUCR5)........................................................ 160 8.3.4 Port Mode Register 5 (PMR5) .......................................................................... 160 8.3.5 Pin Functions .................................................................................................... 161 8.3.6 Input Pull-Up MOS........................................................................................... 162 Port 6................................................................................................................................. 162 8.4.1 Port Data Register 6 (PDR6) ............................................................................ 163 8.4.2 Port Control Register 6 (PCR6) ........................................................................ 163 8.4.3 Port Pull-Up Control Register 6 (PUCR6)........................................................ 164 8.4.4 Pin Functions .................................................................................................... 164 8.4.5 Input Pull-Up MOS........................................................................................... 165 Port 7................................................................................................................................. 165 8.5.1 Port Data Register 7 (PDR7) ............................................................................ 166 8.5.2 Port Control Register 7 (PCR7) ........................................................................ 166 8.5.3 Pin Functions .................................................................................................... 167 Port 8................................................................................................................................. 167 8.6.1 Port Data Register 8 (PDR8) ............................................................................ 168 8.6.2 Port Control Register 8 (PCR8) ........................................................................ 168 8.6.3 Pin Functions .................................................................................................... 168 Port 9................................................................................................................................. 169 8.7.1 Port Data Register 9 (PDR9) ............................................................................ 169 8.7.2 Port Mode Register 9 (PMR9) .......................................................................... 170 8.7.3 Pin Functions .................................................................................................... 170 Port A................................................................................................................................ 171 8.8.1 Port Data Register A (PDRA)........................................................................... 171 8.8.2 Port Control Register A (PCRA) ...................................................................... 172 8.8.3 Pin Functions .................................................................................................... 172 Port B................................................................................................................................ 173 8.9.1 Port Data Register B (PDRB) ........................................................................... 174 8.9.2 Port Mode Register B (PMRB)......................................................................... 174 8.9.3 Pin Functions .................................................................................................... 175 Usage Notes ...................................................................................................................... 176 8.10.1 How to Handle Unused Pin .............................................................................. 176 Section 9 Timers................................................................................................ 177 9.1 9.2 Overview .......................................................................................................................... 177 Timer A............................................................................................................................. 178 9.2.1 Features............................................................................................................. 178 9.2.2 Register Descriptions........................................................................................ 179 9.2.3 Operation .......................................................................................................... 181 Rev. 1.00 Dec. 13, 2007 Page xiv of xviii 9.3 9.4 9.5 9.2.4 Timer A Operating States ................................................................................. 182 Timer F ............................................................................................................................. 182 9.3.1 Features............................................................................................................. 182 9.3.2 Input/Output Pins.............................................................................................. 184 9.3.3 Register Descriptions ........................................................................................ 184 9.3.4 CPU Interface ................................................................................................... 188 9.3.5 Operation .......................................................................................................... 191 9.3.6 Timer F Operating States .................................................................................. 193 9.3.7 Usage Notes ...................................................................................................... 194 Asynchronous Event Counter (AEC)................................................................................ 198 9.4.1 Features............................................................................................................. 198 9.4.2 Input/Output Pins.............................................................................................. 200 9.4.3 Register Descriptions ........................................................................................ 200 9.4.4 Operation .......................................................................................................... 207 9.4.5 Operating States of Asynchronous Event Counter............................................ 212 9.4.6 Usage Notes ...................................................................................................... 213 Watchdog Timer ............................................................................................................... 214 9.5.1 Features............................................................................................................. 214 9.5.2 Register Descriptions ........................................................................................ 215 9.5.3 Operation .......................................................................................................... 217 9.5.4 Operating States of Watchdog Timer................................................................ 218 Section 10 Serial Communication Interface 3 (SCI3) .......................................219 10.1 10.2 10.3 Features............................................................................................................................. 219 Input/Output Pins.............................................................................................................. 221 Register Descriptions........................................................................................................ 221 10.3.1 Receive Shift Register (RSR) ........................................................................... 221 10.3.2 Receive Data Register (RDR) ........................................................................... 222 10.3.3 Transmit Shift Register (TSR) .......................................................................... 222 10.3.4 Transmit Data Register (TDR).......................................................................... 222 10.3.5 Serial Mode Register (SMR) ............................................................................ 223 10.3.6 Serial Control Register 3 (SCR3)...................................................................... 226 10.3.7 Serial Status Register (SSR) ............................................................................. 228 10.3.8 Bit Rate Register (BRR) ................................................................................... 231 10.3.9 Serial Port Control Register (SPCR)................................................................. 237 Operation in Asynchronous Mode .................................................................................... 238 10.4.1 Clock................................................................................................................. 239 10.4.2 SCI3 Initialization............................................................................................. 243 10.4.3 Data Transmission ............................................................................................ 244 10.4.4 Serial Data Reception ....................................................................................... 246 Rev. 1.00 Dec. 13, 2007 Page xv of xviii 10.4 10.5 10.6 10.7 Operation in Clocked Synchronous Mode ........................................................................ 250 10.5.1 Clock................................................................................................................. 250 10.5.2 SCI3 Initialization............................................................................................. 250 10.5.3 Serial Data Transmission .................................................................................. 251 10.5.4 Serial Data Reception ....................................................................................... 254 10.5.5 Simultaneous Serial Data Transmission and Reception.................................... 256 Interrupts........................................................................................................................... 258 Usage Notes ...................................................................................................................... 261 10.7.1 Break Detection and Processing ....................................................................... 261 10.7.2 Mark State and Break Sending ......................................................................... 261 10.7.3 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only).................................................................. 261 10.7.4 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode ..................................................................................... 261 10.7.5 Note on Switching SCK32 Function................................................................. 263 10.7.6 Relation between Writing to TDR and Bit TDRE ............................................ 263 10.7.7 Relation between RDR Reading and bit RDRF................................................ 264 10.7.8 Transmit and Receive Operations when Making State Transition.................... 264 10.7.9 Setting in Subactive or Subsleep Mode ............................................................ 265 Section 11 10-Bit PWM .................................................................................... 267 11.1 11.2 11.3 Features............................................................................................................................. 267 Input/Output Pins.............................................................................................................. 268 Register Descriptions........................................................................................................ 269 11.3.1 PWM Control Register (PWCR) ...................................................................... 269 11.3.2 PWM Data Registers U and L (PWDRU, PWDRL)......................................... 270 Operation .......................................................................................................................... 271 11.4.1 Operation .......................................................................................................... 271 11.4.2 PWM Operating States ..................................................................................... 272 11.4 Section 12 A/D Converter ................................................................................. 273 12.1 12.2 12.3 Features............................................................................................................................. 273 Input/Output Pins.............................................................................................................. 275 Register Descriptions........................................................................................................ 275 12.3.1 A/D Result Registers H and L (ADRRH and ADRRL).................................... 275 12.3.2 A/D Mode Register (AMR) .............................................................................. 276 12.3.3 A/D Start Register (ADSR) .............................................................................. 277 Operation .......................................................................................................................... 277 12.4.1 A/D Conversion ................................................................................................ 277 12.4.2 Operating States of A/D Converter................................................................... 278 12.4 Rev. 1.00 Dec. 13, 2007 Page xvi of xviii 12.5 12.6 12.7 Example of Use................................................................................................................. 278 A/D Conversion Accuracy Definitions ............................................................................. 281 Usage Notes ...................................................................................................................... 283 12.7.1 Permissible Signal Source Impedance .............................................................. 283 12.7.2 Influences on Absolute Accuracy ..................................................................... 283 12.7.3 Additional Usage Notes .................................................................................... 284 Section 13 List of Registers ...............................................................................285 13.1 13.2 13.3 Register Addresses (Address Order)................................................................................. 286 Register Bits...................................................................................................................... 289 Register States in Each Operating Mode .......................................................................... 292 Section 14 Electrical Characteristics .................................................................295 14.1 Absolute Maximum Ratings of H8/38704 Group (Flash Memory Version, Mask ROM Version), H8/38702S Group (Mask ROM Version) ....................................................................................................... 295 Electrical Characteristics of H8/38704 Group (Flash Memory Version, Mask ROM Version), H8/38702S Group (Mask ROM Version) ....................................................................................................... 296 14.2.1 Power Supply Voltage and Operating Ranges .................................................. 296 14.2.2 DC Characteristics ............................................................................................ 301 14.2.3 AC Characteristics ............................................................................................ 311 14.2.4 A/D Converter Characteristics .......................................................................... 315 14.2.5 Flash Memory Characteristics .......................................................................... 317 Operation Timing.............................................................................................................. 319 Output Load Condition ..................................................................................................... 321 Resonator Equivalent Circuit............................................................................................ 321 Usage Note........................................................................................................................ 322 14.2 14.3 14.4 14.5 14.6 Appendix..............................................................................................................323 A. Instruction Set ................................................................................................................... 323 A.1 Instruction List...................................................................................................... 323 A.2 Operation Code Map............................................................................................. 338 A.3 Number of Execution States ................................................................................. 341 A.4 Combinations of Instructions and Addressing Modes .......................................... 352 I/O Port Block Diagrams .................................................................................................. 353 B.1 Port 3 Block Diagrams.......................................................................................... 353 B.2 Port 4 Block Diagrams.......................................................................................... 357 B.3 Port 5 Block Diagram ........................................................................................... 361 B.4 Port 6 Block Diagram ........................................................................................... 362 Rev. 1.00 Dec. 13, 2007 Page xvii of xviii B. C. D. E. B.5 Port 7 Block Diagram ........................................................................................... 363 B.6 Port 8 Block Diagram ........................................................................................... 364 B.7 Port 9 Block Diagrams.......................................................................................... 365 B.8 Port A Block Diagram .......................................................................................... 366 B.9 Port B Block Diagrams ......................................................................................... 367 Port States in Each Operating State .................................................................................. 368 Product Code Lineup ........................................................................................................ 369 Package Dimensions ......................................................................................................... 372 Index ................................................................................................................... 377 Rev. 1.00 Dec. 13, 2007 Page xviii of xviii Section 1 Overview Section 1 Overview 1.1 Features Microcontrollers of the H8/38704 Group and the H8/38702S Group are CISC (complex instruction set computer) microcontrollers whose core is an H8/300H CPU, which has an internal 32-bit architecture. The H8/300H CPU provides upward compatibility with the H8/300 CPUs of other Renesas Technology-original microcontrollers. As peripheral functions, each LSI of these Groups includes various timer functions that realize low-cost configurations for end systems. The power consumption of these modules can be kept down dynamically by power-down mode. 1.1.1 Application Examples of the applications of this LSI include motor control, power meter, and health equipment. Rev. 1.00 Dec. 13, 2007 Page 1 of 380 REJ09B0430-0100 Section 1 Overview 1.1.2 Overview of Specifications Table 1.1 lists the functions of H8/38704, H8/38702S Group products in outline. Table 1.1 Overview of Functions Module/ Function RAM CPU CPU Description * * * * * * * ROM lineup: Flash memory version and mask Rom version ROM capacity: 8 k, 12 k, 16 k, 24 k, and 32 kbytes RAM capacity: 512 and 1024 bytes H8/300H CPU (CISC type) Upward compatibility for H8/300 CPU at object level Sixteen 16-bit general registers Eight addressing modes 64-Kbyte address space Program: 64 Kbytes available Data: 64 Kbytes available * 62 basic instructions, classifiable as bit arithmetic and logic instructions, multiply and divide instructions, bit manipulation instructions, and others Minimum instruction execution time: 400 ns (for an ADD instruction while system clock = 5 MHz and VCC = 2.7 to 3.6 V) On-chip multiplier (16 x 16 32 bits) Normal mode Classification Memory * * Operating mode MCU operating mode Interrupt (source) Interrupt controller (INTC) * Mode: Single-chip mode * * * * Low power consumption state (transition driven by the SLEEP instruction) Eleven external interrupt pins (IRQAEC, IRQ1, IRQ0, WKP7 to WKP0) Seven internal interrupt sources Independent vector addresses Rev. 1.00 Dec. 13, 2007 Page 2 of 380 REJ09B0430-0100 Section 1 Overview Classification Clock Module/ Function Description Two clock generation circuits available Separate clock signals are provided for each of functional modules Includes frequency division circuit, so the operating frequency is selectable Seven low-power-consumption modes: Active (medium speed) mode, sleep (high speed or medium speed) mode, subactive mode, subsleep mode, standby mode, and watch mode 10-bit resolution x four input channels Sample and hold function included Conversion time: 12.4 s per channel (with at 5-MHz operation) Method of starting A/D conversion: software 10 bits x two channels Four conversion periods selectable Pulse division method for less ripple 8-bit timer Interval timer functionality: Eight interrupt periods are selectable Clock time base functionality: Four overflow periods are selectable Generates an interrupt upon overflow 16-bit timer (also can be used as two independent 8-bit timers) Four counter input clocks Output compare function supported Toggle output function supported two interrupt sources: Compare match and overflow 16-bit pulse timer (also can be used as two 8 bits x two channels) Can count asynchronously-input external events Clock pulse * generator * (CPG) * * A/D converter A/D converter (ADC) * * * Timer * 10-bit PWM * * * * Timer A * * * Timer F * * * * * Asynchron- * ous event counter * (AEC) Watchdog timer Watchdog timer (WDT) 8 bits x one channel (selectable from two counter input clocks) Rev. 1.00 Dec. 13, 2007 Page 3 of 380 REJ09B0430-0100 Section 1 Overview Classification Serial interface Module/ Function Serial communications interface 3 (SCI3) Description For both asynchronous and clock synchronous serial communications * Full-duplex communications capability * Select the desired bit rate * Six interrupt sources * Five CMOS input-only pins * 39 CMOS input/output pins * Six large-current-drive pins (port 9) * 23 pull-up resistors * Six open drains * QFP-64: package code: FP-64A (package dimensions: 14 x 14 mm, pin pitch: 0.8 mm) * LQFP-64: package code: FP-64E (package dimensions: 10 x 10 mm, pin pitch: 0.5 mm) * LQFP-64: package code FP-64K (package dimensions: 10 x 10 mm, pin pitch: 0.5 mm) * P-VQFN-64: package code TNP-64B (package dimensions: 8 x 8 mm, pin pitch: 0.4 mm) Packages FP-64E and FP-64K have different package dimensions. For details, see appendix E, Package Dimensions. * Operating frequency: 2 to 10 MHz * Power supply voltage: Flash memory version: Vcc = 2.2 to 3.6 V, AVcc = 2.2 to 3.6 V Mask ROM version: Vcc = 1.8 to 3.6 V, AVcc = 1.8 to 3.6 V * Supply current: Flash memory version: 3.6 mA (typ.) (Vcc = 3.0 V, AVcc = 3.0 V, = 10 MHz) Mask ROM version: 3.1 mA (typ.) (Vcc = 3.0 V, AVcc = 3.0 V, = 10 MHz) * I/O ports Package Operating frequency/ Power supply voltage Operating peripheral temperature (C) * * -20 to +75C (regular specifications) -40 to +85C (wide-range specifications) Rev. 1.00 Dec. 13, 2007 Page 4 of 380 REJ09B0430-0100 Section 1 Overview 1.2 List of Products Table 1.2 and figure 1.1 show the list of products and the structure of a product number, respectively. Table 1.2 Group H8/38704 Group List of Products Product Type HD64F38704 HD64338704 HD64338703 HD64F38702 HD64338702 ROM Size RAM Size Package FP-64A, FP-64E*1, TNP-64B Remarks Flash memory version Mask ROM version Mask ROM version Flash memory version Mask ROM version FP-64A, FP-64K*2, TNP-64B Mask ROM version Mask ROM version Mask ROM version 32 kbytes 1 kbyte 32 kbytes 1 kbyte 24 kbytes 1 kbyte 16 kbytes 1 kbyte 16 kbytes 1 kbyte 16 kbytes 512 bytes 12 kbytes 512 bytes 8 kbytes 512 bytes H8/38702S Group HD64338702S HD64338701S HD64338700S Notes: 1. FP-64E package is only available as an H8/38704 Group microcontroller. 2. FP-64K package is only available as an H8/38702S Group microcontroller. Rev. 1.00 Dec. 13, 2007 Page 5 of 380 REJ09B0430-0100 Section 1 Overview Product type no. HD 64 F 38704 FP Indicates the package. FP: LQFP H: QFP FT: QFN Indicates the product-specific number. H8/38704 Group Indicates the type of ROM device. F: Flash memory 3: Mask ROM Indicates the product family classification H8 Family Indicates the microcontroller. Figure 1.1 How to Read the Product Name Code Rev. 1.00 Dec. 13, 2007 Page 6 of 380 REJ09B0430-0100 Section 1 Overview 1.3 Block Diagram Vss Vss = AVss Vcc RES TEST PA3 PA2 PA1 PA0 IRQAEC X1 X2 Subclock oscillator H8/300H CPU OSC1 OSC2 P31/TMOFL P32/TMOFH P33 P34 P35 P36/AEVH P37/AEVL P40/SCK32 P41/RXD32 P42/TXD32 P43/IRQ0 P50/WKP0 P51/WKP1 P52/WKP2 P53/WKP3 P54/WKP4 P55/WKP5 P56/WKP6 P57/WKP7 P60 P61 P62 P63 P64 P65 P66 P67 System clock oscillator RAM Port 3 Asynchronous event counter (AEC) Port 4 Port 8 Timer A Port 9 ROM Port A P95 P94 P93 P92 P91/PWM2 P90/PWM1 P80 10-bit PWM1 Timer F 10-bit PWM2 P77 P76 P75 P74 P73 P72 P71 P70 PB3/AN3/IRQ1 PB2/AN2 PB1/AN1 PB0/AN0 Port 5 Port 6 10-bit A/D converter Port B SCI3 WDT Port 7 AVcc Notes: When the on-chip emulator is used, pins P95, P33, P34, and P35 are unavailable to the user because they are used exclusively by the on-chip emulator. Figure 1.2 Block Diagram of H8/38704, H8/38702S Group Rev. 1.00 Dec. 13, 2007 Page 7 of 380 REJ09B0430-0100 Section 1 Overview 1.4 Pin Assignment P50/WKP0 P51/WKP1 P52/WKP2 P53/WKP3 P54/WKP4 P55/WKP5 P56/WKP6 P57/WKP7 P60 P61 P62 P63 P64 P65 35 P66 34 48 47 46 45 44 43 42 41 40 39 38 37 36 33 P67 P90/PWM1 P91/PWM2 P92 P93 P94 P95 Vss IRQAEC P40/SCK32 P41/RXD32 P42/TXD32 P43/IRQ0 AVcc PB0/AN0 PB1/AN1 PB2/AN2 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 10 11 12 13 14 15 1 2 3 4 5 6 7 8 9 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 P70 P71 P72 P73 P74 P75 P76 P77 P80 PA0 PA1 PA2 PA3 Vss Vss Vss H8/38704, H8/38702S Group FP-64A, FP-64E, FP-64K, TNP-64B (Top view) P31/TMOFL PB3/IRQ1/AN3 P32/TMOFH X1 X2 OSC2 OSC1 TEST RES P33 P34 P35 P36/AEVH P37/AEVL Note: When the on-chip emulator is used, pins P95, P33, P34, and P35 are unavailable to the user because they are used exclusively by the on-chip emulator. Figure 1.3 Pin Assignment of H8/38704, H8/38702S Group (FP-64A, FP-64E, FP-64K, and TNP-64B) Rev. 1.00 Dec. 13, 2007 Page 8 of 380 REJ09B0430-0100 Vss=AVss Vcc Section 1 Overview 1.5 Table 1.3 Pin Functions Pin Functions Pin No. Type Power source pins Symbol VCC VSS AVCC FP-64A, FP-64E*1, FP-64K*2, TNP-64B I/O 16 4 (= AVSS) 17, 18, 19, 55 61 Input Input Input Functions Power supply pin. Connect this pin to the system power supply. Ground pin. Connect this pin to the system power supply (0V). Analog power supply pin for the A/D converter. When the A/D converter is not used, connect this pin to the system power supply. Ground pin for the A/D converter. Connect this pin to the system power supply (0 V). These pins connect to a crystal or ceramic resonator for system clocks, or can be used to input an external clock. See section 4, Clock Pulse Generators, for a typical connection. AVSS 4 (= VSS) Input Clock pins OSC1 OSC2 6 5 Input Output X1 X2 2 3 Input Output These pins connect to a 32.768- or 38.4-kHz crystal resonator for subclocks. See section 4, Clock Pulse Generators, for a typical connection. System control RES TEST 8 7 Input Input Reset pin. When this driven low, the chip is reset. Test pin. Connect this pin to Vss. Users cannot use this pin. Rev. 1.00 Dec. 13, 2007 Page 9 of 380 REJ09B0430-0100 Section 1 Overview Pin No. Type Interrupt pins Symbol IRQ0 IRQ1 IRQAEC FP-64A, FP-64E*1, FP-64K*2, TNP-64B I/O 60 1 56 Input Input Functions External interrupt request input pins. Can select the rising or falling edge. Asynchronous event counter interrupt input pin. Enables asynchronous event input. Wakeup interrupt request input pins. Can select the rising or falling edge. This is an event input pin for input to the asynchronous event counter. This is an output pin for waveforms generated by the timer FL output compare function. This is an output pin for waveforms generated by the timer FH output compare function. These are output pins for waveforms generated by the channel 1 and 2 10bit PWMs. 7-bit I/O port. Input or output can be designated for each bit by means of the port control register 3 (PCR3). When the on-chip emulator is used, pins P33, P34, and P35 are unavailable to the user because they are used exclusively by the on-chip emulator. 1-bit input port. 3-bit I/O port. Input or output can be designated for each bit by means of the port control register 4 (PCR4). 8-bit I/O port. Input or output can be designated for each bit by means of the port control register 5 (PCR5). WKP7 to WKP0 Timer AEVL AEVH TMOFL 41 to 48 15 14 9 Input Input Output TMOFH 10 Output 10-bit PWM PWM1 PWM2 I/O ports 49 50 Output P37 to P31 15 to 9 I/O P43 60 Input I/O P42 to P40 59 to 57 P57 to P50 41 to 48 I/O Rev. 1.00 Dec. 13, 2007 Page 10 of 380 REJ09B0430-0100 Section 1 Overview Pin No. Type I/O ports Symbol FP-64A, FP-64E*1, FP-64K*2, TNP-64B I/O I/O Functions 8-bit I/O port. Input or output can be designated for each bit by means of the port control register 6 (PCR6). 8-bit I/O port. Input or output can be designated for each bit by means of the port control register 7 (PCR7). 1-bit I/O port. Input or output can be designated for each bit by means of the port control register 8 (PCR8). 6-bit output port. When the on-chip emulator is used, pin P95 is unavailable to the user because it is used exclusively by the on-chip emulator. In the flash memory version, pin P95 should not be open but pulled up to go high in user mode. 4-bit I/O port. Input or output can be designated for each bit by means of the port control register A (PCRA). 4-bit input port. Receive data input pin. Transmit data output pin. Clock I/O pin. Analog data input pins. P67 to P60 33 to 40 P77 to P70 25 to 32 I/O P80 24 I/O P95 to P90 54 to 49 Output PA3 to PA0 PB3 to PB0 Serial com- RXD32 munications TXD32 interface SCK32 (SCI) A/D converter AN3 to AN0 20 to 23 I/O 1, 64 to 62 58 59 57 1, 64 to 62 Input Input Output I/O Input Notes: 1. FP-64E package is only available as an H8/38704 Group microcontroller. 2. FP-64K package is only available as an H8/38702S Group microcontroller. Rev. 1.00 Dec. 13, 2007 Page 11 of 380 REJ09B0430-0100 Section 1 Overview Rev. 1.00 Dec. 13, 2007 Page 12 of 380 REJ09B0430-0100 Section 2 CPU Section 2 CPU This LSI has an H8/300H CPU with an internal 32-bit architecture that is upward-compatible with the H8/300 CPU, and supports only normal mode, which has a 64-kbyte address space. * Upward-compatible with H8/300 CPUs Can execute H8/300 CPUs object programs Additional eight 16-bit extended registers 32-bit transfer and arithmetic and logic instructions are added Signed multiply and divide instructions are added. * General-register architecture Sixteen 16-bit general registers also usable as sixteen 8-bit registers and eight 16-bit registers, or eight 32-bit registers * Sixty-two basic instructions 8/16/32-bit data transfer and arithmetic and logic instructions Multiply and divide instructions Powerful bit-manipulation instructions * Eight addressing modes Register direct [Rn] Register indirect [@ERn] Register indirect with displacement [@(d:16,ERn) or @(d:24,ERn)] Register indirect with post-increment or pre-decrement [@ERn+ or @-ERn] Absolute address [@aa:8, @aa:16, @aa:24] Immediate [#xx:8, #xx:16, or #xx:32] Program-counter relative [@(d:8,PC) or @(d:16,PC)] Memory indirect [@@aa:8] * 64-kbyte address space Rev. 1.00 Dec. 13, 2007 Page 13 of 380 REJ09B0430-0100 Section 2 CPU * High-speed operation All frequently-used instructions execute in one or two states 8/16/32-bit register-register add/subtract : 2 states 8 x 8-bit register-register multiply : 14 states 16 / 8-bit register-register divide : 14 states 16 x 16-bit register-register multiply : 22 states 32 / 16-bit register-register divide : 22 states * Power-down state Transition to power-down state by SLEEP instruction Rev. 1.00 Dec. 13, 2007 Page 14 of 380 REJ09B0430-0100 Section 2 CPU 2.1 Address Space and Memory Map The address space of this LSI is 64 kbytes, which includes the program area and the data area. Figures 2.1 show the memory map. (Flash memory version) H'0000 Interrupt vector area H'0029 H'002A On-chip ROM (32 kbytes) On-chip ROM H'7000 Firmware for on-chip emulator*1 H'7FFF Not used H'F020 Internal I/O register H'F02B H'7FFF (32 kbytes) H'0029 H'002A H'0000 Interrupt vector area (Mask ROM version) Not used Not used H'F780 H'FB7F H'FB80 Working area for flash memory reprogramming*2 (1 kbyte) On-chip RAM (2 kbyte) User area (1 kbyte) Internal I/O register (128 bytes) H'FB80 On-chip RAM (1 kbyte) H'FF7F H'FF80 Internal I/O register (128 bytes) H'FFFF H'FF7F H'FF80 H'FFFF Notes: 1. This area cannot be used by an user when the on-chip emulator is in use. 2. When flash memory is programmed, this area is used by the programming control program. When the on-chip emulator is in use, this area is unavailable to the user. Figure 2.1(1) H8/38704 Memory Map Rev. 1.00 Dec. 13, 2007 Page 15 of 380 REJ09B0430-0100 Section 2 CPU (Mask ROM version) H'0000 Interrupt vector area H'0029 H'002A On-chip ROM (24 kbytes) H'5FFF Not used H'FB80 On-chip RAM (1 bytes) H'FF7F H'FF80 Internal I/O register (128 bytes) H'FFFF Figure 2.1(2) H8/38703 Memory Map Rev. 1.00 Dec. 13, 2007 Page 16 of 380 REJ09B0430-0100 Section 2 CPU (Flash memory version) H'0000 Interrupt vector area H'0029 H'002A On-chip ROM (16 kbytes) H'3FFF Not used H'7000 Firmware for on-chip emulator*1 H'7FFF Not used H'F020 Internal I/O register H'F02B H'3FFF H'0029 H'002A H'0000 (Mask ROM version) Interrupt vector area On-chip ROM (16 kbytes) Not used Not used H'F780 H'FB7F H'FB80 Working area for flash memory reprogramming*2 (1 kbyte) On-chip RAM (2 kbyte) User area (1 kbyte) Internal I/O register (128 bytes) H'FB80 On-chip RAM (1 kbyte) H'FF7F H'FF80 Internal I/O register (128 bytes) H'FFFF H'FF7F H'FF80 H'FFFF Notes: 1. This area cannot be used by an user. 2. When flash memory is programmed, this area is used by the programming control program. When the on-chip emulator is in use, this area is unavailable to the user. Figure 2.1(3) H8/38702 Memory Map Rev. 1.00 Dec. 13, 2007 Page 17 of 380 REJ09B0430-0100 Section 2 CPU (Mask ROM version) H'0000 Interrupt vector area H'0029 H'002A On-chip ROM (16 kbytes) H'3FFF Not used H'FD80 H'FF7F H'FF80 On-chip RAM (512 byte) Internal I/O register (128 bytes) H'FFFF Figure 2.1(4) H8/38702S Memory Map Rev. 1.00 Dec. 13, 2007 Page 18 of 380 REJ09B0430-0100 Section 2 CPU (Mask ROM version) H'0000 Interrupt vector area H'0029 H'002A On-chip ROM (12 kbytes) H'2FFF Not used H'FD80 On-chip RAM (512 bytes) H'FF7F H'FF80 Internal I/O register (128 bytes) H'FFFF Figure 2.1(5) H8/38701S Memory Map Rev. 1.00 Dec. 13, 2007 Page 19 of 380 REJ09B0430-0100 Section 2 CPU (Mask ROM version) H'0000 Interrupt vector area H'0029 H'002A On-chip ROM (8 kbytes) H'1FFF Not used H'FD80 On-chip RAM (512 bytes) H'FF7F H'FF80 H'FFFF Internal I/O register (128 bytes) Figure 2.1(6) H8/38700S Memory Map Rev. 1.00 Dec. 13, 2007 Page 20 of 380 REJ09B0430-0100 Section 2 CPU 2.2 Register Configuration The H8/300H CPU has the internal registers shown in figure 2.2. There are two types of registers; general registers and control registers. The control registers are a 24-bit program counter (PC), and an 8-bit condition-code register (CCR). General Registers (ERn) 15 ER0 ER1 ER2 ER3 ER4 ER5 ER6 ER7 E0 E1 E2 E3 E4 E5 E6 E7 (SP) 07 R0H R1H R2H R3H R4H R5H R6H R7H 07 R0L R1L R2L R3L R4L R5L R6L R7L 0 Control Registers (CR) 23 PC 0 76543210 CCR I UI H U N Z V C [Legend] SP: PC: CCR: I: UI: Stack pointer Program counter Condition-code register Interrupt mask bit User bit H: U: N: Z: V: C: Half-carry flag User bit Negative flag Zero flag Overflow flag Carry flag Figure 2.2 CPU Registers Rev. 1.00 Dec. 13, 2007 Page 21 of 380 REJ09B0430-0100 Section 2 CPU 2.2.1 General Registers The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally identical and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.3 illustrates the usage of the general registers. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7). The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are functionally equivalent, providing a maximum of sixteen 16-bit registers. The E registers (E0 to E7) are also referred to as extended registers. The R registers divide into 8-bit registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are functionally equivalent, providing a maximum of sixteen 8-bit registers. The usage of each register can be selected independently. * Address registers * 32-bit registers * 16-bit registers * 8-bit registers E registers (extended registers) (E0 to E7) ER registers (ER0 to ER7) R registers (R0 to R7) RL registers (R0L to R7L) RH registers (R0H to R7H) Figure 2.3 Usage of General Registers General register ER7 has the function of the stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2.4 shows the relationship between the stack pointer and the stack area. Rev. 1.00 Dec. 13, 2007 Page 22 of 380 REJ09B0430-0100 Section 2 CPU Empty area SP (ER7) Stack area Figure 2.4 Relationship between Stack Pointer and Stack Area 2.2.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched, the least significant PC bit is regarded as 0). The PC is initialized when the start address is loaded by the vector address generated during reset exception-handling sequence. 2.2.3 Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. The I bit is initialized to 1 by reset exception-handling sequence, but other bits are not initialized. Some instructions leave flag bits unchanged. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch (Bcc) instructions. For the action of each instruction on the flag bits, see appendix A.1, Instruction List. Rev. 1.00 Dec. 13, 2007 Page 23 of 380 REJ09B0430-0100 Section 2 CPU Bit 7 Bit Name I Initial Value 1 R/W R/W Description Interrupt Mask Bit Masks interrupts other than NMI when set to 1. NMI is accepted regardless of the I bit setting. The I bit is set to 1 at the start of an exception-handling sequence. 6 UI Undefined R/W User Bit Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. 5 H Undefined R/W Half-Carry Flag When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. 4 U Undefined R/W User Bit Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. 3 N Undefined R/W Negative Flag Stores the value of the most significant bit of data as a sign bit. 2 Z Undefined R/W Zero Flag Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. 1 V Undefined R/W Overflow Flag Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. 0 C Undefined R/W Carry Flag Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by: * * * Add instructions, to indicate a carry Subtract instructions, to indicate a borrow Shift and rotate instructions, to indicate a carry The carry flag is also used as a bit accumulator by bit manipulation instructions. Rev. 1.00 Dec. 13, 2007 Page 24 of 380 REJ09B0430-0100 Section 2 CPU 2.3 Data Formats The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, ..., 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. 2.3.1 General Register Data Formats Figure 2.5 shows the data formats in general registers. Data Type 1-bit data General Register RnH Data Format 7 0 Don't care 7 0 76 54 32 10 1-bit data RnL Don't care 76 54 32 10 7 4-bit BCD data RnH Upper 43 Lower 0 Don't care 7 4-bit BCD data RnL Don't care Upper 43 Lower 0 7 Byte data RnH MSB 0 Don't care LSB 7 0 LSB Byte data RnL Don't care MSB Figure 2.5 General Register Data Formats (1) Rev. 1.00 Dec. 13, 2007 Page 25 of 380 REJ09B0430-0100 Section 2 CPU Data Type Word data General Register Rn Data Format 15 0 Word data En 15 0 MSB LSB MSB LSB 16 15 0 Longword data ERn 31 MSB LSB [Legend] ERn: General register ER En: Rn: General register E General register R RnH: General register RH RnL: General register RL MSB: Most significant bit LSB: Least significant bit Figure 2.5 General Register Data Formats (2) Rev. 1.00 Dec. 13, 2007 Page 26 of 380 REJ09B0430-0100 Section 2 CPU 2.3.2 Memory Data Formats Figure 2.6 shows the data formats in memory. The H8/300H CPU can access word data and longword data in memory, however word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, an address error does not occur, however the least significant bit of the address is regarded as 0, so access begins the preceding address. This also applies to instruction fetches. When ER7 (SP) is used as an address register to access the stack area, the operand size should be word or longword. Data Type Address 7 1-bit data Address L 7 6 5 4 3 2 1 Data Format 0 0 Byte data Address L MSB LSB Word data Address 2M Address 2M+1 MSB LSB Longword data Address 2N Address 2N+1 Address 2N+2 Address 2N+3 MSB LSB Figure 2.6 Memory Data Formats Rev. 1.00 Dec. 13, 2007 Page 27 of 380 REJ09B0430-0100 Section 2 CPU 2.4 2.4.1 Instruction Set Table of Instructions Classified by Function The H8/300H CPU has 62 instructions. Tables 2.2 to 2.9 summarize the instructions in each functional category. The notation used in tables 2.2 to 2.9 is defined in table 2.1. Table 2.1 Symbol Rd Rs Rn ERn (EAd) (EAs) CCR N Z V C PC SP #IMM disp + - x / Operation Notation Description General register (destination)* General register (source)* General register* General register (32-bit register or address register) Destination operand Source operand Condition-code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Program counter Stack pointer Immediate data Displacement Addition Subtraction Multiplication Division Logical AND Logical OR Logical XOR Move NOT (logical complement) Rev. 1.00 Dec. 13, 2007 Page 28 of 380 REJ09B0430-0100 Section 2 CPU Symbol :3/:8/:16/:24 Note: * Description 3-, 8-, 16-, or 24-bit length General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers/address register (ER0 to ER7). Table 2.2 Instruction MOV Data Transfer Instructions Size* B/W/L Function (EAs) Rd, Rs (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. (EAs) Rd Cannot be used in this LSI. Rs (EAs) Cannot be used in this LSI. @SP+ Rn Pops a general register from the stack. POP.W Rn is identical to MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn. Rn @-SP Pushes a general register onto the stack. PUSH.W Rn is identical to MOV.W Rn, @-SP. PUSH.L ERn is identical to MOV.L ERn, @-SP. MOVFPE MOVTPE POP B B W/L PUSH W/L Note: * Refers to the operand size. B: Byte W: Word L: Longword Rev. 1.00 Dec. 13, 2007 Page 29 of 380 REJ09B0430-0100 Section 2 CPU Table 2.3 Instruction ADD SUB Arithmetic Operations Instructions (1) Size* B/W/L Function Rd Rs Rd, Rd #IMM Rd Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register (immediate byte data cannot be subtracted from byte data in a general register. Use the SUBX or ADD instruction.) Rd Rs C Rd, Rd #IMM C Rd Performs addition or subtraction with carry on byte data in two general registers, or on immediate data and data in a general register. Rd 1 Rd, Rd 2 Rd Increments or decrements a general register by 1 or 2. (Byte operands can be incremented or decremented by 1 only.) Rd 1 Rd, Rd 2 Rd, Rd 4 Rd Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register. Rd (decimal adjust) Rd Decimal-adjusts an addition or subtraction result in a general register by referring to the CCR to produce 4-bit BCD data. Rd x Rs Rd Performs unsigned multiplication on data in two general registers: either 8 bits x 8 bits 16 bits or 16 bits x 16 bits 32 bits. Rd x Rs Rd Performs signed multiplication on data in two general registers: either 8 bits x 8 bits 16 bits or 16 bits x 16 bits 32 bits. Rd / Rs Rd Performs unsigned division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8-bit remainder or 32 bits / 16 bits 16-bit quotient and 16-bit remainder. ADDX SUBX INC DEC ADDS SUBS DAA DAS MULXU B B/W/L L B B/W MULXS B/W DIVXU B/W Note: * Refers to the operand size. B: Byte W: Word L: Longword Rev. 1.00 Dec. 13, 2007 Page 30 of 380 REJ09B0430-0100 Section 2 CPU Table 2.3 Instruction DIVXS Arithmetic Operations Instructions (2) Size* B/W Function Rd / Rs Rd Performs signed division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8-bit remainder or 32 bits / 16 bits 16-bit quotient and 16-bit remainder. Rd - Rs, Rd - #IMM Compares data in a general register with data in another general register or with immediate data, and sets CCR bits according to the result. 0 - Rd Rd Takes the two's complement (arithmetic complement) of data in a general register. Rd (zero extension) Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by padding with zeros on the left. Rd (sign extension) Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by extending the sign bit. CMP B/W/L NEG B/W/L EXTU W/L EXTS W/L Note: * Refers to the operand size. B: Byte W: Word L: Longword Rev. 1.00 Dec. 13, 2007 Page 31 of 380 REJ09B0430-0100 Section 2 CPU Table 2.4 Instruction AND Logic Operations Instructions Size* B/W/L Function Rd Rs Rd, Rd #IMM Rd Performs a logical AND operation on a general register and another general register or immediate data. Rd Rs Rd, Rd #IMM Rd Performs a logical OR operation on a general register and another general register or immediate data. Rd Rs Rd, Rd #IMM Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data. (Rd) (Rd) Takes the one's complement (logical complement) of general register contents. OR B/W/L XOR B/W/L NOT B/W/L Note: * Refers to the operand size. B: Byte W: Word L: Longword Table 2.5 Instruction SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR Note: * Shift Instructions Size* B/W/L B/W/L B/W/L B/W/L Function Rd (shift) Rd Performs an arithmetic shift on general register contents. Rd (shift) Rd Performs a logical shift on general register contents. Rd (rotate) Rd Rotates general register contents. Rd (rotate) Rd Rotates general register contents through the carry flag. Refers to the operand size. B: Byte W: Word L: Longword Rev. 1.00 Dec. 13, 2007 Page 32 of 380 REJ09B0430-0100 Section 2 CPU Table 2.6 Instruction BSET Bit Manipulation Instructions Size* B Function 1 ( BCLR B BNOT B BTST B BAND B BIAND B BOR B BIOR B BXOR B BIXOR B Rev. 1.00 Dec. 13, 2007 Page 33 of 380 REJ09B0430-0100 Section 2 CPU Instruction BLD Size* B Function ( BILD B BST B BIST B Note: * Refers to the operand size. B: Byte Rev. 1.00 Dec. 13, 2007 Page 34 of 380 REJ09B0430-0100 Section 2 CPU Table 2.7 Instruction Bcc* Branch Instructions Size Function Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic BRA(BT) BRN(BF) BHI BLS BCC(BHS) BCS(BLO) BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE Description Always (true) Never (false) High Low or same Carry clear (high or same) Carry set (low) Not equal Equal Overflow clear Overflow set Plus Minus Greater or equal Less than Greater than Less or equal Condition Always Never CZ=0 CZ=1 C=0 C=1 Z=0 Z=1 V=0 V=1 N=0 N=1 NV=0 NV=1 Z(N V) = 0 Z(N V) = 1 JMP BSR JSR RTS Note: * Branches unconditionally to a specified address. Branches to a subroutine at a specified address. Branches to a subroutine at a specified address. Returns from a subroutine Bcc is the general name for conditional branch instructions. Rev. 1.00 Dec. 13, 2007 Page 35 of 380 REJ09B0430-0100 Section 2 CPU Table 2.8 Instruction RTE SLEEP LDC System Control Instructions Size* B/W Function Returns from an exception-handling routine. Causes a transition to a power-down state. (EAs) CCR Moves the source operand contents to the CCR. The CCR size is one byte, but in transfer from memory, data is read by word access. CCR (EAd) Transfers the CCR contents to a destination location. The condition code register size is one byte, but in transfer to memory, data is written by word access. CCR #IMM CCR Logically ANDs the CCR with immediate data. CCR #IMM CCR Logically ORs the CCR with immediate data. CCR #IMM CCR Logically XORs the CCR with immediate data. PC + 2 PC Only increments the program counter. STC B/W ANDC ORC XORC NOP Note: * B B B Refers to the operand size. B: Byte W: Word Rev. 1.00 Dec. 13, 2007 Page 36 of 380 REJ09B0430-0100 Section 2 CPU Table 2.9 Instruction EEPMOV.B Block Data Transfer Instructions Size Function if R4L 0 then Repeat @ER5+ @ER6+, R4L-1 R4L Until R4L = 0 else next; if R4 0 then Repeat @ER5+ @ER6+, R4-1 R4 Until R4 = 0 else next; Transfers a data block. Starting from the address set in ER5, transfers data for the number of bytes set in R4L or R4 to the address location set in ER6. Execution of the next instruction begins as soon as the transfer is completed. EEPMOV.W Rev. 1.00 Dec. 13, 2007 Page 37 of 380 REJ09B0430-0100 Section 2 CPU 2.4.2 Basic Instruction Formats H8/300H CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op), a register field (r), an effective address extension (EA), and a condition field (cc). Figure 2.7 shows examples of instruction formats. (1) Operation Field Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. The operation field always includes the first four bits of the instruction. Some instructions have two operation fields. (2) Register Field Specifies a general register. Address registers are specified by 3 bits, and data registers by 3 bits or 4 bits. Some instructions have two register fields. Some have no register field. (3) Effective Address Extension 8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. A24-bit address or displacement is treated as a 32-bit data in which the first 8 bits are 0 (H'00). (4) Condition Field Specifies the branching condition of Bcc instructions. (1) Operation field only op (2) Operation field and register fields op rn rm ADD.B Rn, Rm, etc. NOP, RTS, etc. (3) Operation field, register fields, and effective address extension op EA(disp) (4) Operation field, effective address extension, and condition field op cc EA(disp) BRA d:8 rn rm MOV.B @(d:16, Rn), Rm Figure 2.7 Instruction Formats Rev. 1.00 Dec. 13, 2007 Page 38 of 380 REJ09B0430-0100 Section 2 CPU 2.5 Addressing Modes and Effective Address Calculation The following describes the H8/300H CPU. In this LSI, the upper eight bits are ignored in the generated 24-bit address, so the effective address is 16 bits. 2.5.1 Addressing Modes The H8/300H CPU supports the eight addressing modes listed in table 2.10. Each instruction uses a subset of these addressing modes. Addressing modes that can be used differ depending on the instruction. For details, refer to appendix A.4, Combinations of Instructions and Addressing Modes. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except program-counter relative and memory indirect. Bit-manipulation instructions use register direct, register indirect, or the absolute addressing mode (@aa:8) to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. Table 2.10 Addressing Modes No. 1 2 3 4 5 6 7 8 Addressing Mode Register direct Register indirect Register indirect with displacement Register indirect with post-increment Register indirect with pre-decrement Absolute address Immediate Program-counter relative Memory indirect Symbol Rn @ERn @(d:16,ERn)/@(d:24,ERn) @ERn+ @-ERn @aa:8/@aa:16/@aa:24 #xx:8/#xx:16/#xx:32 @(d:8,PC)/@(d:16,PC) @@aa:8 (1) Register DirectRn The register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers. Rev. 1.00 Dec. 13, 2007 Page 39 of 380 REJ09B0430-0100 Section 2 CPU (2) Register Indirect@ERn The register field of the instruction code specifies an address register (ERn), the lower 24 bits of which contain the address of the operand on memory. (3) Register Indirect with Displacement@(d:16, ERn) or @(d:24, ERn) A 16-bit or 24-bit displacement contained in the instruction is added to an address register (ERn) specified by the register field of the instruction, and the lower 24 bits of the sum the address of a memory operand. A 16-bit displacement is sign-extended when added. (4) Register Indirect with Post-Increment or Pre-Decrement@ERn+ or @-ERn * Register indirect with post-increment@ERn+ The register field of the instruction code specifies an address register (ERn) the lower 24 bits of which contains the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents (32 bits) and the sum is stored in the address register. The value added is 1 for byte access, 2 for word access, or 4 for longword access. For the word or longword access, the register value should be even. * Register indirect with pre-decrement@-ERn The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field in the instruction code, and the lower 24 bits of the result is the address of a memory operand. The result is also stored in the address register. The value subtracted is 1 for byte access, 2 for word access, or 4 for longword access. For the word or longword access, the register value should be even. (5) Absolute Address@aa:8, @aa:16, @aa:24 The instruction code contains the absolute address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24) For an 8-bit absolute address, the upper 16 bits are all assumed to be 1 (H'FFFF). For a 16-bit absolute address the upper 8 bits are a sign extension. A 24-bit absolute address can access the entire address space. The access ranges of absolute addresses for this LSI are those shown in table 2.11, because the upper 8 bits are ignored. Rev. 1.00 Dec. 13, 2007 Page 40 of 380 REJ09B0430-0100 Section 2 CPU Table 2.11 Absolute Address Access Ranges Absolute Address 8 bits (@aa:8) 16 bits (@aa:16) 24 bits (@aa:24) Access Range H'FF00 to H'FFFF H'0000 to H'FFFF H'0000 to H'FFFF (6) Immediate#xx:8, #xx:16, or #xx:32 The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. (7) Program-Counter Relative@(d:8, PC) or @(d:16, PC) This mode is used in the BSR instruction. An 8-bit or 16-bit displacement contained in the instruction is sign-extended and added to the 24-bit PC contents to generate a branch address. The PC value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is -126 to +128 bytes (-63 to +64 words) or -32766 to +32768 bytes (-16383 to +16384 words) from the branch instruction. The resulting value should be an even number. (8) Memory Indirect@@aa:8 This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand. This memory operand contains a branch address. The memory operand is accessed in words, generating a 16-bit branch address. Figure 2.8 shows how to specify branch address for in memory indirect mode. The upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255 (H'0000 to H'00FF). Note that the first part of the address range is also the exception vector area. Rev. 1.00 Dec. 13, 2007 Page 41 of 380 REJ09B0430-0100 Section 2 CPU Specified by @aa:8 Branch address Figure 2.8 Branch Address Specification in Memory Indirect Mode Rev. 1.00 Dec. 13, 2007 Page 42 of 380 REJ09B0430-0100 Section 2 CPU 2.5.2 Effective Address Calculation Table 2.12 indicates how effective addresses are calculated in each addressing mode. In this LSI, the upper 8 bits of the effective address are ignored in order to generate a 16-bit effective address. Table 2.12 Effective Address Calculation (1) No 1 Addressing Mode and Instruction Format Register direct(Rn) Effective Address Calculation Effective Address (EA) Operand is general register contents. op 2 rm rn 31 General register contents Register indirect(@ERn) 0 23 0 op 3 r Register indirect with displacement @(d:16,ERn) or @(d:24,ERn) 31 General register contents 0 23 0 op r disp 31 Sign extension 0 disp 4 Register indirect with post-increment or pre-decrement *Register indirect with post-increment @ERn+ 31 General register contents 0 23 0 op r 31 1, 2, or 4 *Register indirect with pre-decrement @-ERn 0 General register contents 23 0 op r 1, 2, or 4 The value to be added or subtracted is 1 when the operand is byte size, 2 for word size, and 4 for longword size. Rev. 1.00 Dec. 13, 2007 Page 43 of 380 REJ09B0430-0100 Section 2 CPU Table 2.12 Effective Address Calculation (2) No 5 Addressing Mode and Instruction Format Absolute address Effective Address Calculation Effective Address (EA) @aa:8 op abs 23 H'FFFF 87 0 @aa:16 op abs 23 16 15 0 Sign extension @aa:24 op abs 23 0 6 Immediate #xx:8/#xx:16/#xx:32 op IMM Operand is immediate data. 7 Program-counter relative @(d:8,PC)/@(d:16,PC) 23 PC contents 0 op disp 23 Sign extension 0 disp 23 0 8 Memory indirect @@aa:8 23 op abs H'0000 15 87 abs 0 0 Memory contents 23 16 15 H'00 0 [Legend] r, rm,rn : op : disp : IMM : abs : Register field Operation field Displacement Immediate data Absolute address Rev. 1.00 Dec. 13, 2007 Page 44 of 380 REJ09B0430-0100 Section 2 CPU 2.6 Basic Bus Cycle CPU operation is synchronized by a system clock () or a subclock (SUB). The period from a rising edge of or SUB to the next rising edge is called one state. A bus cycle consists of two states or three states. The cycle differs depending on whether access is to on-chip memory or to on-chip peripheral modules. 2.6.1 Access to On-Chip Memory (RAM, ROM) Access to on-chip memory takes place in two states. The data bus width is 16 bits, allowing access in byte or word size. Figure 2.9 shows the on-chip memory access cycle. Bus cycle T1 state or SUB T2 state Internal address bus Address Internal read signal Internal data bus (read access) Read data Internal write signal Internal data bus (write access) Write data Figure 2.9 On-Chip Memory Access Cycle Rev. 1.00 Dec. 13, 2007 Page 45 of 380 REJ09B0430-0100 Section 2 CPU 2.6.2 On-Chip Peripheral Modules On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits or 16 bits depending on the register. For description on the data bus width and number of accessing states of each register, refer to section 13.1, Register Addresses (Address Order). Registers with 16-bit data bus width can be accessed by word size only. Registers with 8-bit data bus width can be accessed by byte or word size. When a register with 8-bit data bus width is accessed by word size, a bus cycle occurs twice. In two-state access, the operation timing is the same as that for on-chip memory. Figure 2.10 shows the operation timing in the case of three-state access to an on-chip peripheral module. Bus cycle T1 state or SUB T2 state T3 state Internal address bus Internal read signal Internal data bus (read access) Internal write signal Internal data bus (write access) Address Read data Write data Figure 2.10 On-Chip Peripheral Module Access Cycle (3-State Access) Rev. 1.00 Dec. 13, 2007 Page 46 of 380 REJ09B0430-0100 Section 2 CPU 2.7 CPU States There are four CPU states: the reset state, program execution state, program halt state, and exception-handling state. The program execution state includes active (high-speed or mediumspeed) mode and subactive mode. For the program halt state, there are sleep (high-speed or medium-speed) mode, standby mode, watch mode, and subsleep mode. These states are shown in figure 2.11. Figure 2.12 shows the state transitions. For details on program execution state and program halt state, refer to section 5, Power-Down Modes. For details on exception handling, refer to section 3, Exception Handling. CPU state Reset state The CPU is initialized Program execution state Active (high-speed) mode The CPU executes successive program instructions at high speed, synchronized by the system clock Active (medium-speed) mode The CPU executes successive program instructions at reduced speed, synchronized by the system clock Subactive mode The CPU executes successive program instructions at reduced speed, synchronized by the subclock Program halt state A state in which the CPU operation is stopped to reduce power consumption Sleep (high-speed) mode Sleep (medium-speed) mode Standby mode Watch mode Subsleep mode Exception-handling state A transient state in which the CPU changes the processing flow due to a reset or an interrupt Figure 2.11 CPU Operating States Rev. 1.00 Dec. 13, 2007 Page 47 of 380 REJ09B0430-0100 Power-down modes Section 2 CPU Reset cleared Reset state Reset occurs Exception-handling state Reset occurs Reset occurs Interrupt source Interrupt source Exceptionhandling complete Program halt state SLEEP instruction executed Program execution state Figure 2.12 State Transitions 2.8 2.8.1 Usage Notes Notes on Data Access to Empty Areas The address space of this LSI includes empty areas in addition to the ROM, RAM, and on-chip I/O registers areas available to the user. When data is transferred from CPU to empty areas, the transferred data will be lost. This action may also cause the CPU to malfunction. When data is transferred from an empty area to CPU, the contents of the data cannot be guaranteed. 2.8.2 EEPMOV Instruction EEPMOV is a block-transfer instruction and transfers the byte size of data indicated by R4L, which starts from the address indicated by R5, to the address indicated by R6. Set R4L and R6 so that the end address of the destination address (value of R6 + R4L) does not exceed H'FFFF (the value of R6 must not change from H'FFFF to H'0000 during execution). Rev. 1.00 Dec. 13, 2007 Page 48 of 380 REJ09B0430-0100 Section 2 CPU 2.8.3 Bit-Manipulation Instruction The BSET, BCLR, BNOT, BST, and BIST instructions read data from the specified address in byte units, manipulate the data of the target bit, and write data to the same address again in byte units. Special care is required when using these instructions in cases where two registers are assigned to the same address, or when a bit is directly manipulated for a port or a register containing a write-only bit, because this may rewrite data of a bit other than the bit to be manipulated. (1) Bit manipulation for two registers assigned to the same address Example 1: Bit manipulation for the timer load register and timer counter Figure 2.13 shows an example of a timer in which two timer registers are assigned to the same address. When a bit-manipulation instruction accesses the timer load register and timer counter of a reloadable timer, since these two registers share the same address, the following operations takes place. 1. Data is read in byte units. 2. The CPU sets or resets the bit to be manipulated with the bit-manipulation instruction. 3. The written data is written again in byte units to the timer load register. The timer is counting, so the value read is not necessarily the same as the value in the timer load register. As a result, bits other than the intended bit in the timer counter may be modified and the modified value may be written to the timer load register. Read Count clock Timer counter Reload Write Timer load register Internal data bus Figure 2.13 Example of Timer Configuration with Two Registers Allocated to Same Address Rev. 1.00 Dec. 13, 2007 Page 49 of 380 REJ09B0430-0100 Section 2 CPU Example 2: When the BSET instruction is executed for port 5 P57 and P56 are input pins, with a low-level signal input at P57 and a high-level signal input at P56. P55 to P50 are output pins and output low-level signals. An example to output a high-level signal at P50 with a BSET instruction is shown below. * Prior to executing BSET instruction P57 Input/output Pin state PCR5 PDR5 Input Low level 0 1 P56 Input High level 0 0 P55 Output Low level 1 0 P54 Output Low level 1 0 P53 Output Low level 1 0 P52 Output Low level 1 0 P51 Output Low level 1 0 P50 Output Low level 1 0 * BSET instruction executed BSET #0, @PDR5 The BSET instruction is executed for port 5. * After executing BSET instruction P57 Input/output Pin state PCR5 PDR5 Input Low level 0 0 P56 Input High level 0 1 P55 Output Low level 1 0 P54 Output Low level 1 0 P53 Output Low level 1 0 P52 Output Low level 1 0 P51 Output Low level 1 0 P50 Output High level 1 1 * Description on operation 1. When the BSET instruction is executed, first the CPU reads port 5. Since P57 and P56 are input pins, the CPU reads the pin states (low-level and high-level input). P55 to P50 are output pins, so the CPU reads the value in PDR5. In this example PDR5 has a value of H'80, but the value read by the CPU is H'40. 2. Next, the CPU sets bit 0 of the read data to 1, changing the PDR5 data to H'41. Rev. 1.00 Dec. 13, 2007 Page 50 of 380 REJ09B0430-0100 Section 2 CPU 3. Finally, the CPU writes H'41 to PDR5, completing execution of BSET instruction. As a result of the BSET instruction, bit 0 in PDR5 becomes 1, and P50 outputs a high-level signal. However, bits 7 and 6 of PDR5 end up with different values. To prevent this problem, store a copy of the PDR5 data in a work area in memory. Perform the bit manipulation on the data in the work area, then write this data to PDR5. * Prior to executing BSET instruction MOV.B MOV.B MOV.B #H'80, R0L R0L, @RAM0 R0L, @PDR5 P57 Input/output Pin state PCR5 PDR5 RAM0 Input Low level 0 1 1 P56 Input High level 0 0 0 The PDR5 value (H'80) is written to a work area in memory (RAM0) as well as to PDR5. P55 Output Low level 1 0 0 P54 Output Low level 1 0 0 P53 Output Low level 1 0 0 P52 Output Low level 1 0 0 P51 Output Low level 1 0 0 P50 Output Low level 1 0 0 * BSET instruction executed BSET #0, @RAM0 The BSET instruction is executed designating the PDR5 work area (RAM0). * After executing BSET instruction MOV.B MOV.B @RAM0, R0L R0L, @PDR5 P57 Input/output Pin state PCR5 PDR5 RAM0 Input Low level 0 1 1 P56 Input High level 0 0 0 The work area (RAM0) value is written to PDR5. P55 Output Low level 1 0 0 P54 Output Low level 1 0 0 P53 Output Low level 1 0 0 P52 Output Low level 1 0 0 P51 Output Low level 1 0 0 P50 Output High level 1 1 1 Rev. 1.00 Dec. 13, 2007 Page 51 of 380 REJ09B0430-0100 Section 2 CPU (2) Bit Manipulation in a Register Containing a Write-Only Bit Example 3: BCLR instruction executed designating port 5 control register PCR5 P57 and P56 are input pins, with a low-level signal input at P57 and a high-level signal input at P56. P55 to P50 are output pins that output low-level signals. An example of setting the P50 pin as an input pin by the BCLR instruction is shown below. It is assumed that a high-level signal will be input to this input pin. * Prior to executing BCLR instruction P57 Input/output Pin state PCR5 PDR5 Input Low level 0 1 P56 Input High level 0 0 P55 Output Low level 1 0 P54 Output Low level 1 0 P53 Output Low level 1 0 P52 Output Low level 1 0 P51 Output Low level 1 0 P50 Output Low level 1 0 * BCLR instruction executed BCLR #0, @PCR5 The BCLR instruction is executed for PCR5. * After executing BCLR instruction P57 Input/output Pin state PCR5 PDR5 Output Low level 1 1 P56 Output High level 1 0 P55 Output Low level 1 0 P54 Output Low level 1 0 P53 Output Low level 1 0 P52 Output Low level 1 0 P51 Output Low level 1 0 P50 Input High level 0 0 * Description on operation 1. When the BCLR instruction is executed, first the CPU reads PCR5. Since PCR5 is a write-only register, the CPU reads a value of H'FF, even though the PCR5 value is actually H'3F. 2. Next, the CPU clears bit 0 in the read data to 0, changing the data to H'FE. 3. Finally, H'FE is written to PCR5 and BCLR instruction execution ends. As a result of this operation, bit 0 in PCR5 becomes 0, making P50 an input port. However, bits 7 and 6 in PCR5 change to 1, so that P57 and P56 change from input pins to output pins. To prevent this problem, store a copy of the PDR5 data in a work area in memory and manipulate data of the bit in the work area, then write this data to PDR5. Rev. 1.00 Dec. 13, 2007 Page 52 of 380 REJ09B0430-0100 Section 2 CPU * Prior to executing BCLR instruction MOV.B MOV.B MOV.B #H'3F, R0L R0L, @RAM0 R0L, @PCR5 P57 Input/output Pin state PCR5 PDR5 RAM0 Input Low level 0 1 0 P56 Input High level 0 0 0 The PCR5 value (H'3F) is written to a work area in memory (RAM0) as well as to PCR5. P55 Output Low level 1 0 1 P54 Output Low level 1 0 1 P53 Output Low level 1 0 1 P52 Output Low level 1 0 1 P51 Output Low level 1 0 1 P50 Output Low level 1 0 1 * BCLR instruction executed BCLR #0, @RAM0 The BCLR instructions executed for the PCR5 work area (RAM0). * After executing BCLR instruction MOV.B MOV.B @RAM0, R0L R0L, @PCR5 P57 Input/output Pin state PCR5 PDR5 RAM0 Input Low level 0 1 0 P56 Input High level 0 0 0 The work area (RAM0) value is written to PCR5. P55 Output Low level 1 0 1 P54 Output Low level 1 0 1 P53 Output Low level 1 0 1 P52 Output Low level 1 0 1 P51 Output Low level 1 0 1 P50 Output High level 0 0 0 Rev. 1.00 Dec. 13, 2007 Page 53 of 380 REJ09B0430-0100 Section 2 CPU Rev. 1.00 Dec. 13, 2007 Page 54 of 380 REJ09B0430-0100 Section 3 Exception Handling Section 3 Exception Handling Exception handling may be caused by a reset or interrupts. * Reset A reset has the highest exception priority. Exception handling starts as soon as the reset is cleared by the RES pin. The chip is also reset when the watchdog timer overflows, and exception handling starts. Exception handling is the same as exception handling by the RES pin. * Interrupts External interrupts and internal interrupts are masked by the I bit in CCR, and kept masked while the I bit is set to 1. Exception handling starts when the current instruction or exception handling ends, if an interrupt request has been issued. The following notes apply to the HD64F38704 and HD64F38702. * Issue Depending on the circuitry status at power-on, a vector 17 (system reservation) interrupt request may be generated. If bit I in CCR is cleared to 0, this interrupt will be accepted just like any other internal interrupt. This can cause processing exceptions to occur, and program execution will eventually halt since there is no procedure for clearing the interrupt request flag in question. * Countermeasure To prevent the above issue from occurring, it is recommended that the following steps be added to programs written for the product. Rev. 1.00 Dec. 13, 2007 Page 55 of 380 REJ09B0430-0100 Section 3 Exception Handling Reset Initialize stack pointer Write H'9E to H'FFC3 Read H'FFC3 Write H'F1 to H'FFC3 Write H'BF to H'FFFA Clear I bit in CCR User program Additional steps Rev. 1.00 Dec. 13, 2007 Page 56 of 380 REJ09B0430-0100 Section 3 Exception Handling The following is an example in assembler. .ORG H'0000 .DATA.W INIT .ORG H'0100 INIT: MOV.W #H'FF80:16,SP MOV.B MOV.B MOV.B MOV.B MOV.B MOV.B MOV.B ANDC.B #H'9E:8,R0L R0L,@H'FFC3:8 @H'FFC3:8,R0L #H'F1:8,R0L R0L,@H'FFC3:8 #H'BF:8,R0L R0L,@H'FFFA:8 #H'7F:8,CCR ; user program The following is an example in C. void powerON_Reset(void) { // ------------------------------------------------------unsigned char dummy; *((volatile unsigned char *)0xffc3)= 0x9e; dummy = *((volatile unsigned char *)0xffc3); *((volatile unsigned char *)0xffc3)= 0xf1; *((volatile unsigned char *)0xfffa)= 0xbf; // ------------------------------------------------------set_imask_ccr(0); // clear I bit // user program } On the mask ROM version of the product, user programs may be used as is (including the additional steps described above) or without the additional steps. Rev. 1.00 Dec. 13, 2007 Page 57 of 380 REJ09B0430-0100 Section 3 Exception Handling 3.1 Exception Sources and Vector Address Table 3.1 shows the vector addresses and priority of each exception handling. When more than one interrupt is requested, handling is performed from the interrupt with the highest priority. Table 3.1 Exception Sources and Vector Address Exception Sources Reset Reserved for system use IRQ0 IRQ1 IRQAEC External interrupt pin Reserved for system use WKP0 WKP1 WKP2 WKP3 WKP4 WKP5 WKP6 WKP7 Reserved for system use Timer A overflow Asynchronous event counter overflow Reserved for system use Timer FL compare match Timer FL overflow Timer FH compare match Timer FH overflow SCI3 Reserved for system use Transmit end Transmit data empty Transmit data full Receive error A/D conversion end Direct transition by SLEEP instruction Vector Number 0 1 to 3 4 5 6 7, 8 9 Vector Address H'0000 to H'0001 H'0002 to H'0007 H'0008 to H'0009 H'000A to H'000B H'000C to H'000D H'000E to H'0011 H'0012 to H'0013 Priority High Relative Module RES pin, WDT External interrupt pin Timer A Asynchronous event counter Timer F 10 11 12 13 14 15 16, 17 18 H'0014 to H'0015 H'0016 to H'0017 H'0018 to H'0019 H'001A to H'001B H'001C to H'001D H'001E to H'001F H'0020 to H'0023 H'0024 to H'0025 A/D converter CPU 19 20 H'0026 to H'0027 H'0028 to H'0029 Low Rev. 1.00 Dec. 13, 2007 Page 58 of 380 REJ09B0430-0100 Section 3 Exception Handling 3.2 Register Descriptions Interrupts are controlled by the following registers. * * * * * * * Interrupt edge select register (IEGR) Interrupt enable register 1 (IENR1) Interrupt enable register 2 (IENR2) Interrupt request register 1 (IRR1) Interrupt request register 2 (IRR2) Wakeup interrupt request register (IWPR) Wakeup edge select register (WEGR) Interrupt Edge Select Register (IEGR) 3.2.1 IEGR selects the direction of an edge that generates interrupt requests of pins and IRQ1 and IRQ0. Bit 7 to 5 4 to 2 1 0 Bit Name IEG1 IEG0 Initial Value All 1 0 0 R/W W R/W R/W Description Reserved These bits are always read as 1. Reserved The write value should always be 0. IRQ1 and IRQ0 Edge Select 0: Falling edge of IRQn pin input is detected 1: Rising edge of IRQn pin input is detected (n = 1 or 0) Rev. 1.00 Dec. 13, 2007 Page 59 of 380 REJ09B0430-0100 Section 3 Exception Handling 3.2.2 Interrupt Enable Register 1 (IENR1) IENR1 enables timers and external pin interrupts. Bit 7 Bit Name IENTA Initial Value 0 R/W R/W Description Timer A interrupt enable Enables or disables timer A overflow interrupt requests. 0: Disables timer A interrupt requests 1: Enables timer A interrupt requests 6 5 IENWP 0 W R/W Reserved The write value should always be 0. Wakeup Interrupt Enable Enables or disables WKP7 to WKP0 interrupt requests. 0: Disables WKP7 to WKP0 interrupt requests 1: Enables WKP7 to WKP0 interrupt requests 4, 3 2 IENEC2 0 W R/W Reserved The write value should always be 0. IRQAEC Interrupt Enable Enables or disables IRQAEC interrupt requests. 0: Disables IRQAEC interrupt requests 1: Enables IRQAEC interrupt requests 1 0 IEN1 IEN0 0 0 R/W R/W IRQ1 and IRQ0 Interrupt Enable Enables or disables IRQ1 and IRQ0 interrupt requests. 0: Disables IRQn interrupt requests 1: Enables IRQn interrupt requests (n = 1, 0) Rev. 1.00 Dec. 13, 2007 Page 60 of 380 REJ09B0430-0100 Section 3 Exception Handling 3.2.3 Interrupt Enable Register 2 (IENR2) IENR2 enables direct transition, A/D converter, and timer interrupts. Bit 7 Bit Name IENDT Initial Value 0 R/W R/W Description Direct Transition Interrupt enable Enables or disables direct transition interrupt requests. 0: Disables direct transition interrupt requests 1: Enables direct transition interrupt requests 6 IENAD 0 R/W A/D Converter Interrupt enable Enables or disables A/D conversion end interrupt requests. 0: Disables A/D converter interrupt requests 1: Enables A/D converter interrupt requests 5, 4 3 IENTFH 0 W R/W Reserved The write value should always be 0. Timer FH Interrupt Enable Enables or disables timer FH compare match or overflow interrupt requests. 0: Disables timer FH interrupt requests 1: Enables timer FH interrupt requests 2 IENTFL 0 R/W Timer FL Interrupt Enable Enables or disables timer FL compare match or overflow interrupt requests. 0: Disables timer FL interrupt requests 1: Enables timer FL interrupt requests 1 0 IENEC 0 W R/W Reserved The write value should always be 0. Asynchronous Event Counter Interrupt Enable Enables or disables asynchronous event counter interrupt requests. 0: Disables asynchronous event counter interrupt requests 1: Enables asynchronous event counter interrupt requests For details on SCI3 interrupt control, refer to section 10.3.6, Serial Control Register 3 (SCR3). Rev. 1.00 Dec. 13, 2007 Page 61 of 380 REJ09B0430-0100 Section 3 Exception Handling 3.2.4 Interrupt Request Register 1 (IRR1) IRR1 is a status flag register for timer A, IRQAEC, IRQ1, and IRQ0 interrupt requests. The corresponding flag is set to 1 when an interrupt request occurs. The flags are not cleared automatically when an interrupt is accepted. It is necessary to write 0 to clear each flag. Bit 7 Bit Name IRRTA Initial Value 0 R/W R/W* Description Timer A Interrupt Request Flag [Setting condition] When the timer A counter value overflows [Clearing condition] When IRRTA = 1, it is cleared by writing 0 6, 4, 3 5 2 IRREC2 1 0 W R/W* Reserved The write value should always be 0. Reserved This bit is always read as 1 and cannot be modified. IRQAEC Interrupt Request Flag [Setting condition] When pin IRQAEC is designated for interrupt input and the designated signal edge is detected [Clearing condition] When IRREC2 = 1, it is cleared by writing 0 1 0 IRRl1 IRRl0 0 0 R/W* R/W* IRQ1 and IRQ0 Interrupt Request Flag [Setting condition] When pin IRQn is designated for interrupt input and the designated signal edge is detected (n = 1, 0) [Clearing condition] When IRRI1 and IRRI0 = 1, they are cleared by writing 0 Note: * Only 0 can be written for flag clearing. Rev. 1.00 Dec. 13, 2007 Page 62 of 380 REJ09B0430-0100 Section 3 Exception Handling 3.2.5 Interrupt Request Register 2 (IRR2) IRR2 is a status flag register for direct transition, A/D converter, timer FH, timer FL, and asynchronous event counter interrupt requests. The corresponding flag is set to 1 when an interrupt request occurs. The flags are not cleared automatically when an interrupt is accepted. It is necessary to write 0 to clear each flag. Bit 7 Bit Name IRRDT Initial Value 0 R/W R/W* Description Direct Transition Interrupt Request Flag [Setting condition] When a direct transition is made by executing a SLEEP instruction while the DTON bit = 1 [Clearing condition] When IRRDT = 1, it is cleared by writing 0 6 IRRAD 0 R/W* A/D Converter Interrupt Request Flag [Setting condition] When A/D conversion is completed and the ADSF bit is cleared to 0 [Clearing condition] When IRRAD = 1, it is cleared by writing 0 5, 4 3 IRRTFH 0 W R/W* Reserved The write value should always be 0. Timer FH Interrupt Request Flag [Setting condition] When TCFH and OCRFH match in 8-bit timer mode, or when TCF (TCFL, TCFH) and OCRF (OCRFL, OCRFH) match in 16-bit timer mode [Clearing condition] When IRRTFH = 1, it is cleared by writing 0 2 IRRTFL 0 R/W* Timer FL Interrupt Request Flag [Setting condition] When TCFL and OCRFL match in 8-bit timer mode [Clearing condition] When IRRTFL = 1, it is cleared by writing 0 1 W Reserved The write value should always be 0. Rev. 1.00 Dec. 13, 2007 Page 63 of 380 REJ09B0430-0100 Section 3 Exception Handling Bit 0 Bit Name IRREC Initial Value 0 R/W R/W* Description Asynchronous Event Counter Interrupt Request Flag [Setting condition] When ECH overflows in 16-bit counter mode, or ECH or ECL overflows in 8-bit counter mode [Clearing condition] When IRREC = 1, it is cleared by writing 0 Note: * Only 0 can be written for flag clearing. 3.2.6 Wakeup Interrupt Request Register (IWPR) IWPR is a status flag register for WKP7 to WKP0 interrupt requests. The flags are not cleared automatically when an interrupt is accepted. It is necessary to write 0 to clear each flag. Bit 7 6 5 4 3 2 1 0 Note: * Bit Name IWPF7 IWPF6 IWPF5 IWPF4 IWPF3 IWPF2 IWPF1 IWPF0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* Description Wakeup Interrupt Request Flag 7 to 0 [Setting condition] When pin WKPn is designated for wakeup input and the designated edge is detected (n = 7 to 0) [Clearing condition] When IWPFn= 1, it is cleared by writing 0 Only 0 can be written for flag clearing. Rev. 1.00 Dec. 13, 2007 Page 64 of 380 REJ09B0430-0100 Section 3 Exception Handling 3.2.7 Wakeup Edge Select Register (WEGR) Initial Value 0 0 0 0 0 0 0 0 WEGR specifies rising or falling edge sensing for pins WKPn. Bit 7 6 5 4 3 2 1 0 Bit Name WKEGS7 WKEGS6 WKEGS5 WKEGS4 WKEGS3 WKEGS2 WKEGS1 WKEGS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description WKPn Edge Select 7 to 0 Selects WKPn pin input sensing. 0: WKPn pin falling edge is detected 1: WKPn pin rising edge is detected (n = 7 to 0) 3.3 Reset Exception Handling When the RES pin goes low, all processing halts and this LSI enters the reset. The internal state of the CPU and the registers of the on-chip peripheral modules are initialized by the reset. To ensure that this LSI is reset at power-on, hold the RES pin low until the clock pulse generator output stabilizes. To reset the chip during operation, hold the RES pin low for at least 10 system clock cycles. When the RES pin goes high after being held low for the necessary time, this LSI starts reset exception handling. The reset exception handling sequence is shown in figure 3.1. The reset exception handling sequence is as follows. 1. Set the I bit in the condition code register (CCR) to 1. 2. The CPU generates a reset exception handling vector address (from H'0000 to H'0001), the data in that address is sent to the program counter (PC) as the start address, and program execution starts from that address. Rev. 1.00 Dec. 13, 2007 Page 65 of 380 REJ09B0430-0100 Section 3 Exception Handling 3.4 3.4.1 Interrupt Exception Handling External Interrupts There are external interrupts, WKP7 to WKP0, IRQ1, IRQ0, and IRQAEC. (1) WKP7 to WKP0 Interrupts WKP7 to WKP0 interrupts are requested by input signals to pins WKP7 to WKP0. These interrupts have the same vector addresses, and are detected individually by either rising edge sensing or falling edge sensing, depending on the settings of bits WKEGS7 to WKEGS0 in WEGR. When pins WKP7 to WKP0 are designated for interrupt input in PMR5 and the designated signal edge is input, the corresponding bit in IWPR is set to 1, requesting the CPU of an interrupt. These interrupts can be masked by setting bit IENWP in IENR1. (2) IRQ1 and IRQ0 Interrupts IRQ1 and IRQ0 interrupts are requested by input signals to pins IRQ1 and IRQ0. These interrupts are given different vector addresses, and are detected individually by either rising edge sensing or falling edge sensing, depending on the settings of bits IEG1 and IEG0 in IEGR. When pins IRQ1 and IRQ0 are designated for interrupt input by PMRB and PMR2 and the designated signal edge is input, the corresponding bit in IRR1 is set to 1, requesting the CPU of an interrupt. These interrupts can be masked by setting bits IEN1 and IEN0 in IENR1. (3) IRQAEC Interrupt The IRQAEC interrupt is requested by an input signal to pin IRQAEC. This interrupt is detected by either rising edge sensing or falling edge sensing, depending on the settings of bits AIEGS1 and AIEGS0 in AEGSR. When bit IENEC2 in IENR1 is designated for interrupt input and the designated signal edge is input, the corresponding bit in IRR1 is set to 1, requesting the CPU of an interrupt. Rev. 1.00 Dec. 13, 2007 Page 66 of 380 REJ09B0430-0100 Section 3 Exception Handling Reset cleared Initial program instruction prefetch Vector fetch Internal processing RES Internal address bus Internal read signal Internal write signal Internal data bus (16 bits) (1) (2) (2) (3) (1) Reset exception handling vector address (H'0000) (2) Program start address (3) Initial program instruction Figure 3.1 Reset Sequence 3.4.2 Internal Interrupts Each on-chip peripheral module has a flag to show the interrupt request status and the enable bit to enable or disable the interrupt. For direct transition interrupt requests generated by execution of a SLEEP instruction, this function is included in IRR1 and IRR2. When an on-chip peripheral module requests an interrupt, the corresponding interrupt request status flag is set to 1, requesting the CPU of an interrupt. When this interrupt is accepted, the I bit is set to 1 in CCR. These interrupts can be masked by writing 0 to clear the corresponding enable bit. Rev. 1.00 Dec. 13, 2007 Page 67 of 380 REJ09B0430-0100 Section 3 Exception Handling 3.4.3 Interrupt Handling Sequence Interrupts are controlled by an interrupt controller. Interrupt operation is described as follows. 1. If an interrupt occurs while the interrupt enable bit is set to 1, an interrupt request signal is sent to the interrupt controller. 2. When multiple interrupt requests are generated, the interrupt controller requests to the CPU for the interrupt handling with the highest priority at that time according to table 3.1. Other interrupt requests are held pending. 3. Interrupt requests are accepted, if the I bit is cleared to 0 in CCR; if the I bit is set to 1, the interrupt request is held pending. 4. If the CPU accepts the interrupt after processing of the current instruction is completed, interrupt exception handling will begin. First, both PC and CCR are pushed onto the stack. The state of the stack at this time is shown in figure 3.2. The PC value pushed onto the stack is the address of the first instruction to be executed upon return from interrupt handling. 5. Then, the I bit in CCR is set to 1, masking further interrupts. Upon return from interrupt handling, the values of I bit and other bits in CCR will be restored and returned to the values prior to the start of interrupt exception handling. 6. Next, the CPU generates the vector address corresponding to the accepted interrupt, and transfers the address to PC as a start address of the interrupt handling-routine. Then a program starts executing from the address indicated in PC. Figure 3.3 shows a typical interrupt sequence where the program area is in the on-chip ROM and the stack area is in the on-chip RAM. Notes: 1. When disabling interrupts by clearing bits in the interrupt enable register, or when clearing bits in the interrupt request register, always do so while interrupts are masked (I = 1). 2. If the above clear operations are performed while I = 0, and as a result a conflict arises between the clear instruction and an interrupt request, exception processing for the interrupt will be executed after the clear instruction has been executed. Rev. 1.00 Dec. 13, 2007 Page 68 of 380 REJ09B0430-0100 Section 3 Exception Handling SP - 4 SP - 3 SP - 2 SP - 1 SP (R7) Stack area SP (R7) SP + 1 SP + 2 SP + 3 SP + 4 CCR CCR* PCH PCL Even address Prior to start of interrupt exception handling PC and CCR saved to stack After completion of interrupt exception handling [Legend] PCH : Upper 8 bits of program counter (PC) PCL : Lower 8 bits of program counter (PC) CCR: Condition code register SP: Stack pointer Notes: PC shows the address of the first instruction to be executed upon return from the interrupt handling routine. Register contents must always be saved and restored by word length, starting from an even-numbered address. * Ignored when returning from the interrupt handling routine. Figure 3.2 Stack Status after Exception Handling 3.4.4 Interrupt Response Time Table 3.2 shows the number of wait states after an interrupt request flag is set until the first instruction of the interrupt handling-routine is executed. Table 3.2 Item Waiting time for completion of executing instruction* Saving of PC and CCR to stack Vector fetch Instruction fetch Internal processing Note: * Not including EEPMOV instruction. Interrupt Wait States States 1 to 13 4 2 4 4 Total 15 to 27 Rev. 1.00 Dec. 13, 2007 Page 69 of 380 REJ09B0430-0100 REJ09B0430-0100 Interrupt is accepted Instruction prefetch Internal processing Stack access Vector fetch Prefetch instruction of Internal interrupt-handling routine processing (1) (3) (5) (6) (8) (9) (2) (4) (1) (7) (9) (10) Section 3 Exception Handling Interrupt level decision and wait for end of instruction Interrupt request signal Rev. 1.00 Dec. 13, 2007 Page 70 of 380 Internal address bus Internal read signal Internal write signal Figure 3.3 Interrupt Sequence Internal data bus (16 bits) (1) Instruction prefetch address (Instruction is not executed. Address is saved as PC contents, becoming return address.) (2)(4) Instruction code (not executed) (3) Instruction prefetch address (Instruction is not executed.) (5) SP - 2 (6) SP - 4 (7) CCR (8) Vector address (9) Starting address of interrupt-handling routine (contents of vector) (10) First instruction of interrupt-handling routine Section 3 Exception Handling 3.5 3.5.1 Usage Notes Interrupts after Reset If an interrupt is accepted after a reset and before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests are disabled immediately after a reset. Since the first instruction of a program is always executed immediately after the reset state ends, make sure that this instruction initializes the stack pointer (example: MOV.W #xx: 16, SP). 3.5.2 Notes on Stack Area Use When word data is accessed, the least significant bit of the address is regarded as 0. Access to the stack always takes place in word size, so the stack pointer (SP: R7) should never indicate an odd address. Use PUSH Rn (MOV.W Rn, @-SP) or POP Rn (MOV.W @SP+, Rn) to save or restore register values. 3.5.3 Interrupt Request Flag Clearing Method Use the following recommended method for flag clearing in the interrupt request registers (IRR1, IRR2, and IWPR). Recommended Method: Perform flag clearing with only one instruction. Either a bit manipulation instruction or a data transfer instruction in bytes can be used. Two examples of coding for clearing IRRI1 (bit 1 in IRR1) are shown below: * BCR #1,@IRR1:8 * MOV.B R1L,@IRR1:8 (Set B11111101 to R1L in advance) Malfunction Example: When flag clearing is performed with several instructions, a flag, other than the intended one, which was set while executing one of those instructions may be accidentally cleared, and thus cause incorrect operations to occur. An example of coding for clearing IRRI1 (bit 1 in IRR1), in which IRRI0 is also cleared and the interrupt becomes invalid is shown below. MOV.B @IRR1:8,R1L AND.B #B11111101,R1L MOV.B R1L,@IRR1:8 At this point, IRRI0 is 0. IRRI0 becomes 1 here. IRRI0 is cleared to 0. Rev. 1.00 Dec. 13, 2007 Page 71 of 380 REJ09B0430-0100 Section 3 Exception Handling In the above example, an IRQ0 interrupt occurs while the AND.B instruction is executed. Since not only the original target IRRI1, but also IRRI0 is cleared to 0, the IRQ0 interrupt becomes invalid. 3.5.4 Notes on Rewriting Port Mode Registers When a port mode register is rewritten to switch the functions of external interrupt pins, IRQAEC, IRQ1, IRQ0, and WKP7 to WKP0, the interrupt request flag may be set to 1. When switching a pin function, mask the interrupt before setting the bit in the port mode register. After accessing the port mode register, execute at least one instruction (e.g., NOP), then clear the interrupt request flag from 1 to 0. Table 3.3 lists the interrupt request flags which are set to 1 and the conditions. Table 3.3 Conditions under which Interrupt Request Flag is Set to 1 Interrupt Request Flags Set to 1 Conditions IRR1 IRREC2 IRRI1 When the edge designated by AIEGS1 and AIEGS0 in AEGSR is input while IENEC2 in IENRI is set to 1. When IRQ1 bit in PMRB is changed from 0 to 1 while pin IRQ1 is low and IEG1 bit in IEGR = 0. When IRQ1 bit in PMRB is changed from 1 to 0 while pin IRQ1 is low and IEG1 bit in IEGR = 1. IRRI0 When IRQ0 bit in PMR2 is changed from 0 to 1 while pin IRQ0 is low and IEG0 bit in IEGR = 0. When IRQ0 bit in PMR2 is changed from 1 to 0 while pin IRQ0 is low and IEG0 bit in IEGR = 1. Rev. 1.00 Dec. 13, 2007 Page 72 of 380 REJ09B0430-0100 Section 3 Exception Handling Interrupt Request Flags Set to 1 Conditions IWPR IWPF7 When PMR5 bit WKP7 is changed from 0 to 1 while pin WKP7 is low and WEGR bit WKEGS7 = 0. When PMR5 bit WKP7 is changed from 1 to 0 while pin WKP7 is low and WEGR bit WKEGS7 = 1. IWPF6 When PMR5 bit WKP6 is changed from 0 to 1 while pin WKP6 is low and WEGR bit WKEGS6 = 0. When PMR5 bit WKP6 is changed from 1 to 0 while pin WKP6 is low and WEGR bit WKEGS6 = 1. IWPF5 When PMR5 bit WKP5 is changed from 0 to 1 while pin WKP5 is low and WEGR bit WKEGS5 = 0. When PMR5 bit WKP5 is changed from 1 to 0 while pin WKP5 is low and WEGR bit WKEGS5 = 1. IWPF4 When PMR5 bit WKP4 is changed from 0 to 1 while pin WKP4 is low and WEGR bit WKEGS4 = 0. When PMR5 bit WKP4 is changed from 1 to 0 while pin WKP4 is low and WEGR bit WKEGS4 = 1. IWPF3 When PMR5 bit WKP3 is changed from 0 to 1 while pin WKP3 is low and WEGR bit WKEGS3 = 0. When PMR5 bit WKP3 is changed from 1 to 0 while pin WKP3 is low and WEGR bit WKEGS3 = 1. IWPF2 When PMR5 bit WKP2 is changed from 0 to 1 while pin WKP2 is low and WEGR bit WKEGS2 = 0. When PMR5 bit WKP2 is changed from 1 to 0 while pin WKP2 is low and WEGR bit WKEGS2 = 1. IWPF1 When PMR5 bit WKP1 is changed from 0 to 1 while pin WKP1 is low and WEGR bit WKEGS1 = 0. When PMR5 bit WKP1 is changed from 1 to 0 while pin WKP1 is low and WEGR bit WKEGS1 = 1. IWPF0 When PMR5 bit WKP0 is changed from 0 to 1 while pin WKP0 is low and WEGR bit WKEGS0 = 0. When PMR5 bit WKP0 is changed from 1 to 0 while pin WKP0 is low and WEGR bit WKEGS0 = 1. Rev. 1.00 Dec. 13, 2007 Page 73 of 380 REJ09B0430-0100 Section 3 Exception Handling Figure 3.4 shows a port mode register setting and interrupt request flag clearing procedure. Interrupts masked. (Another possibility is to disable the relevant interrupt in interrupt enable register 1.) CCR I bit 1 Set port mode register bit Execute NOP instruction Clear interrupt request flag to 0 After setting the port mode register bit, first execute at least one instruction (e.g., NOP), then clear the interrupt request flag to 0 CCR I bit 0 Interrupt mask cleared Figure 3.4 Port Mode Register Setting and Interrupt Request Flag Clearing Procedure Rev. 1.00 Dec. 13, 2007 Page 74 of 380 REJ09B0430-0100 Section 4 Clock Pulse Generators Section 4 Clock Pulse Generators 4.1 Features Clock oscillator circuitry (CPG: clock pulse generator) is provided on-chip, including both a system clock pulse generator and a subclock pulse generator. The system clock pulse generator consists of a system clock oscillator and system clock dividers. The subclock pulse generator consists of a subclock oscillator and a subclock divider. Figure 4.1 shows a block diagram of the clock pulse generators. OSC/2 OSC1 OSC2 System clock oscillator OSC (fOSC) System clock divider (1/2) OSC/16 OSC/32 OSC/64 OSC/128 Prescaler S (13bits) System clock divider System clock pulse generator W/2 W (fW) Subclock divider (1/2, 1/4, 1/8) W/4 W/8 /2 to /8192 W X1 X2 Subclock oscillator SUB W/2 W/4 Prescaler W (5bits) Subclock pulse generator W/8 to W/128 Figure 4.1 Block Diagram of Clock Pulse Generators Rev. 1.00 Dec. 13, 2007 Page 75 of 380 REJ09B0430-0100 Section 4 Clock Pulse Generators 4.2 System Clock Generator Clock pulses can be supplied to the system clock divider either by connecting a crystal or ceramic resonator, or by providing external clock input. Figure 4.2 shows a block diagram of the system clock generator. OSC2 LPM OSC1 Note: LPM: Power-down mode (standby mode, subactive mode, subsleep mode, watch mode) Figure 4.2 Block Diagram of System Clock Generator 4.2.1 Connecting Crystal Resonator Figure 4.3 shows a typical method of connecting a crystal oscillator to the H8/38704, H8/38702S Group. Figure 4.4 shows the equivalent circuit of a crystal resonator. A resonator having the characteristics given in table 4.1 should be used. C1 OSC1 Rf OSC2 C2 4.0 MHz Frequency Manufacturer Prodoct Name C1, C2 Recommendation Value 12 pF 20% KYOCERA KINSEKI Corp. HC-49/U-S Rf = 1 M 20% Note: Consult with the crystal resonator manufacturer to determine the circuit constants. Figure 4.3 Typical Connection to Crystal Resonator (H8/38704, H8/38702S Group) LS RS CS OSC1 C0 OSC2 Figure 4.4 Equivalent Circuit of Crystal Resonator Rev. 1.00 Dec. 13, 2007 Page 76 of 380 REJ09B0430-0100 Section 4 Clock Pulse Generators Table 4.1 Crystal Resonator Parameters 4.10 150 1.4 pF 4.193 Frequency (MHz) RS (max) C0 (max) 4.2.2 Connecting Ceramic Resonator Figure 4.5 shows a typical method of connecting a ceramic oscillator to the H8/38704, H8/38702S Group. C1 OSC1 Rf OSC2 Ceramic resonator Frequency C2 2.0 MHz Murata Manufacturing Co., CSTCC2M00G53-B0 Ltd. CSTCC2M00G56-B0 CSTLS4MAG53-B0 CSTLS4MAG56-B0 Manufacturer Product Name C1, C2 Recommendation Value 15 pF 20% 47 pF 20% 15 pF 0.5% 47 pF 0.5% 15 pF 20% 47 pF 20% 4.19 MHz 10.0 MHz CSTLS10M0G53-B0 CSTLS10M0G56-B0 Rf = 1 M 20% Notes: Consult with the ceramic resonator manufacturer to determine the circuit constants. Figure 4.5 Typical Connection to Ceramic Resonator (H8/38704, H8/38702S Group) 4.2.3 External Clock Input Method Connect an external clock signal to pin OSC1, and leave pin OSC2 open. Figure 4.6 shows a typical connection. The duty cycle of the external clock signal must be 45 to 55%. OSC1 External clock input OSC2 Open Figure 4.6 Example of External Clock Input Rev. 1.00 Dec. 13, 2007 Page 77 of 380 REJ09B0430-0100 Section 4 Clock Pulse Generators 4.3 Subclock Generator Figure 4.7 shows a block diagram of the subclock generator. X2 10 M X1 Note : Resistance is a reference value. Figure 4.7 Block Diagram of Subclock Generator 4.3.1 Connecting 32.768-kHz/38.4-kHz Crystal Resonator Clock pulses can be supplied to the subclock divider by connecting a 32.768-kHz or 38.4-kHz crystal resonator, as shown in figure 4.8. Figure 4.9 shows the equivalent circuit of the 32.768kHz or 38.4-kHz crystal resonator. C1 X1 C1 = C 2 = 7 pF (typ.) C2 X2 Frequency 38.4 kHz 32.768 kHz Manufacturer EPSON TOYOCOM Corp. EPSON TOYOCOM Corp. Product Name Equivalent Series Resistance C-4-TYPE C-001R 30 k (max.) 35 k (max.) Notes: 1. When using a resonator other than the above, ensure optimal conditions by conducting sufficient evaluation of consistency in cooperation with the manufacturer of the resonator. Even if the above resonators or products equivalent to them are implemented, their oscillation characteristics are affected by the board design. Be sure to use the actual board to evaluate consistency as a system. 2. The consistency as a system has to be verified not only in a reset state (i.e., the RES pin is driven low) but also in a state where a reset state has been exited (i.e., the low-level RES signal has been driven high). Figure 4.8 Typical Connection to 32.768-kHz/38.4-kHz Crystal Resonator Rev. 1.00 Dec. 13, 2007 Page 78 of 380 REJ09B0430-0100 Section 4 Clock Pulse Generators LS CS RS X1 CO X2 CO = 0.9 pF (typ.) RS = 14 k (typ.) fW = 32.768 kHz/38.4 kHz Note: Constants are reference values. Figure 4.9 Equivalent Circuit of 32.768-kHz/38.4-kHz Crystal Resonator 4.3.2 Pin Connection when Not Using Subclock When the subclock is not used, connect pin X1 to GND and leave pin X2 open, as shown in figure 4.10. X1 GND X2 Open Figure 4.10 Pin Connection when Not Using Subclock Rev. 1.00 Dec. 13, 2007 Page 79 of 380 REJ09B0430-0100 Section 4 Clock Pulse Generators 4.3.3 External Clock Input Connect the external clock to pin X1 and leave pin X2 open, as shown in figure 4.11. X1 External clock input X2 Open Figure 4.11 Pin Connection when Inputting External Clock Frequency Duty Subclock (w) 45% to 55% 4.4 4.4.1 Prescalers Prescaler S Prescaler S is a 13-bit counter using the system clock () as its input clock. It is incremented once per clock period. Prescaler S is initialized to H'0000 by a reset, and starts counting on exit from the reset state. In standby mode, watch mode, subactive mode, and subsleep mode, the system clock pulse generator stops. Prescaler S also stops and is initialized to H'0000. The CPU cannot read or write prescaler S. The output from prescaler S is shared by the on-chip peripheral modules. The division ratio can be set separately for each on-chip peripheral function. In active (mediumspeed) mode and sleep mode, the clock input to prescaler S is determined by the division ratio designated by the MA1 and MA0 bits in SYSCR2. 4.4.2 Prescaler W Prescaler W is a 5-bit counter using a 32.768 kHz or 38.4 kHz signal divided by 4 (W/4) as its input clock. The divided output is used for clock time base operation of timer A. Prescaler W is initialized to H'00 by a reset, and starts counting on exit from the reset state. Even in standby mode, watch mode, subactive mode, or subsleep mode, prescaler W continues functioning. Prescaler W can be reset by setting 1s in bits TMA3 and TMA2 in TMA. Rev. 1.00 Dec. 13, 2007 Page 80 of 380 REJ09B0430-0100 Section 4 Clock Pulse Generators 4.5 4.5.1 Usage Notes Note on Resonators Resonator characteristics are closely related to board design and should be carefully evaluated by the user, referring to the examples shown in this section. Resonator circuit constants will differ depending on the resonator element, stray capacitance in its interconnecting circuit, and other factors. Suitable constants should be determined in consultation with the resonator manufacturer. Design the circuit so that the resonator never receives voltages exceeding its maximum rating. PB3 X1 X2 Vss OSC2 OSC1 TEST (Vss) Figure 4.12 Example of Crystal and Ceramic Resonator Arrangement Figure 4.13 (1) shows an example of the measurement circuit for the negative resistor which is recommended by the resonator manufacturer. Note that if the negative resistor in this circuit does not reach the level which is recommended by the resonator manufacturer, the main oscillator may be hard to start oscillation. If the negative resistor does not reach the level which is recommended by the resonator manufacturer and oscillation is not started, changes as shown in figure 4.13 (2) to (4) should be made. The proposed change and capacitor size to be applied should be determined according to the evaluation result of the negative resistor and frequency deviation, etc. Rev. 1.00 Dec. 13, 2007 Page 81 of 380 REJ09B0430-0100 Section 4 Clock Pulse Generators Change OSC1 C1 Rf OSC1 C1 Rf OSC2 C2 Negative resistor -R added (1) Negative resistor measurement circuit C2 OSC2 (2) Proposed Change in Oscillator Circuit 1 Change Change OSC1 C1 Rf C3 OSC1 C1 Rf OSC2 C2 (3) Proposed Change in Oscillator Circuit 2 C2 OSC2 (4) Proposed Change in Oscillator Circuit 3 Figure 4.13 Negative Resistor Measurement and Proposed Changes in Circuit 4.5.2 Notes on Board Design When using a crystal resonator (ceramic resonator), place the resonator and its load capacitors as close as possible to the OSC1 and OSC2 pins. Other signal lines should be routed away from the resonator circuit to prevent induction from interfering with correct oscillation (see figure 4.14). Avoid Signal A Signal B C1 OSC1 C2 OSC2 Figure 4.14 Example of Incorrect Board Design Rev. 1.00 Dec. 13, 2007 Page 82 of 380 REJ09B0430-0100 Section 4 Clock Pulse Generators 4.5.3 Definition of Oscillation Stabilization Standby Time Figure 4.15 shows the oscillation waveform (OSC2), system clock (), and microcomputer operating mode when a transition is made from standby mode, watch mode, or subactive mode, to active (high-speed/medium-speed) mode, with a resonator connected to the system clock oscillator. As shown in figure 4.15, as the system clock oscillator is halted in standby mode, watch mode, and subactive mode, when a transition is made to active (high-speed/medium-speed) mode, the sum of the following two times (oscillation stabilization time and standby time) is required. 1. Oscillation start time The time from the point at which the oscillation waveform of the system clock oscillator starts to change when an interrupt is generated, until generation of the system clock is started. 2. Standby time The time required for the CPU and peripheral functions to begin operating after generation of the system clock has been started. The standby time setting is selected with standby timer select bits 2 to 0 (STS2 to STS0) (bits 6 to 4 in the system control register 1 (SYSCR1)). Rev. 1.00 Dec. 13, 2007 Page 83 of 380 REJ09B0430-0100 Section 4 Clock Pulse Generators Oscillation waveform (OSC2) System clock () Oscillation start time Standby time Standby mode, Operating mode watch mode, or subactive mode Oscillation stabilization standby time Active (high-speed) mode or active (medium-speed) mode Interrupt accepted Figure 4.15 Oscillation Stabilization Standby Time The required oscillation stabilization time is identical with the oscillation stabilization time (trc) when power as specified by the AC characteristics is supplied. The setting must be such that the time specified by the STS2 to STS0 bits in SYSCR is not less than trc. Consequently, when a resonator is connected as the system clock oscillator and a transition is made from the standby, watch, or subactive mode to the active (high- or medium-speed) mode, be sure to sufficiently test behavior on the actual circuit. Waiting time must be enough for the amplitudes of OSC1 and OSC2 to become sufficiently large. Since the oscillation start time varies with the constant of the actual circuit and stray capacitance, determine the oscillation stabilization waiting time in close cooperation with the manufacturer of the resonator. Rev. 1.00 Dec. 13, 2007 Page 84 of 380 REJ09B0430-0100 Section 4 Clock Pulse Generators 4.5.4 Notes on Use of Resonator When a microcomputer operates, the internal power supply potential fluctuates slightly in synchronization with the system clock. Depending on the individual resonator characteristics, the oscillation waveform amplitude may not be sufficiently large immediately after the oscillation stabilization standby time, making the oscillation waveform susceptible to influence by fluctuations in the power supply potential. In this state, the oscillation waveform may be disrupted, leading to an unstable system clock and erroneous operation of the microcomputer. If erroneous operation occurs, change the setting of standby timer select bits 2 to 0 (STS2 to STS0) (bits 6 to 4 in system control register 1 (SYSCR1)) to give a longer standby time. For example, if erroneous operation occurs with a standby time setting of 1,024 states, check the operation with a standby time setting of 2,048 states or more. If the same kind of erroneous operation occurs after a reset as after a state transition, hold the RES pin low for a longer period. Rev. 1.00 Dec. 13, 2007 Page 85 of 380 REJ09B0430-0100 Section 4 Clock Pulse Generators Rev. 1.00 Dec. 13, 2007 Page 86 of 380 REJ09B0430-0100 Section 5 Power-Down Modes Section 5 Power-Down Modes This LSI has eight modes of operation after a reset. These include a normal active (high-speed) mode and seven power-down modes, in which power consumption is significantly reduced. The module standby function reduces power consumption by selectively halting on-chip module functions. * Active (medium-speed) mode The CPU and all on-chip peripheral modules are operable on the system clock. The system clock frequency can be selected from osc/16, osc/32, osc/64, and osc/128. * Subactive mode The CPU and all on-chip peripheral modules are operable on the subclock. The subclock frequency can be selected from w/2, w/4, and w/8. * Sleep (high-speed) mode The CPU halts. On-chip peripheral modules are operable on the system clock. * Sleep (medium-speed) mode The CPU halts. On-chip peripheral modules are operable on the system clock. The system clock frequency can be selected from osc/16, osc/32, osc/64, and osc/128. * Subsleep mode The CPU halts. The timer A, timer F, SCI3, and AEC are operable on the subclock. The subclock frequency can be selected from w/2, w/4, and w/8. * Watch mode The CPU halts. Timer A's timekeeping function, timer F, and AEC are operable on the subclock. * Standby mode The CPU and all on-chip peripheral modules halt. * Module standby function Independent of the above modes, power consumption can be reduced by halting on-chip peripheral modules that are not used in module units. Note: In this manual, active (high-speed) mode and active (medium-speed) mode are collectively called active mode. Rev. 1.00 Dec. 13, 2007 Page 87 of 380 REJ09B0430-0100 Section 5 Power-Down Modes 5.1 Register Descriptions The registers related to power-down modes are as follows. * System control register 1 (SYSCR1) * System control register 2 (SYSCR2) * Clock halt registers 1 and 2 (CKSTPR1 and CKSTPR2) 5.1.1 System Control Register 1 (SYSCR1) SYSCR1 controls the power-down modes, as well as SYSCR2. Bit 7 Bit Name SSBY Initial Value 0 R/W R/W Description Software Standby Selects the mode to transit after the execution of the SLEEP instruction. 0: A transition is made to sleep mode or subsleep mode. 1: A transition is made to standby mode or watch mode. For details, see table 5.2. 6 5 4 STS2 STS1 STS0 0 0 0 R/W R/W R/W Standby Timer Select 2 to 0 Designate the time the CPU and peripheral modules wait for stable clock operation after exiting from standby mode, subactive mode, subsleep mode, or watch mode to active mode or sleep mode due to an interrupt. The designation should be made according to the operating frequency so that the waiting time is at least equal to the oscillation stabilization time. The relationship between the specified value and the number of wait states is shown in table 5.1. When an external clock is to be used, the minimum value (STS2 = 1, STS1 = 0, STS0 = 1) is recommended. If the setting other than the recommended value is made, operation may start before the end of the waiting time. 3 LSON 0 R/W Selects the system clock () or subclock (SUB) as the CPU operating clock when watch mode is cleared. 0: The CPU operates on the system clock () 1: The CPU operates on the subclock (SUB) Rev. 1.00 Dec. 13, 2007 Page 88 of 380 REJ09B0430-0100 Section 5 Power-Down Modes Bit 2 1 0 Bit Name MA1 MA0 Initial Value 1 1 1 R/W R/W R/W Description Reserved This bit is always read as 1 and cannot be modified. Active Mode Clock Select 1 and 0 Select OSC/16, OSC/32, OSC/64, or OSC/128 as the operating clock in active (medium-speed) mode and sleep (medium-speed) mode. The MA1 and MA0 bits should be written to in active (high-speed) mode or subactive mode. 00: OSC/16 01: OSC/32 10: OSC/64 11: OSC/128 Table 5.1 Operating Frequency and Waiting Time Bit Operating Frequency STS0 0 1 1 0 1 Waiting Time 8,192 states 16,384 states 1,024 states 2,048 states 4,096 states 2 states (external clock input) 8 states 16 states 5 MHz 1.638 3.277 0.205 0.410 0.819 0.0004 0.002 0.003 2 MHz 4.1 8.2 0.512 1.024 2.048 0.001 0.004 0.008 STS2 0 STS1 0 1 0 0 1 1 0 1 Note: The time unit is ms. If external clock input is used, STS2 to STS0 should be set to the external clock input mode before the mode transition is executed. In addition, STS2 to STS0 should not be set to the external clock input mode if external clock input is not used. Rev. 1.00 Dec. 13, 2007 Page 89 of 380 REJ09B0430-0100 Section 5 Power-Down Modes 5.1.2 System Control Register 2 (SYSCR2) SYSCR2 controls the power-down modes, as well as SYSCR1. Bit 7 to 5 Bit Name Initial Value All 1 R/W Description Reserved These bits are always read as 1 and cannot be modified. 4 NESEL 1 R/W Noise Elimination Sampling Frequency Select Selects the frequency at which the watch clock signal (W) generated by the subclock pulse generator is sampled, in relation to the oscillator clock (OSC) generated by the system clock pulse generator. When OSC = 2 to 16 MHz, clear this bit to 0. 0: Sampling rate is OSC/16. 1: Sampling rate is OSC/4. 3 DTON 0 R/W Direct Transfer on Flag Selects the mode to which the transition is made after the SLEEP instruction is executed with bits SSBY and LSON in SYSCR1, bit MSON in SYSCR2, and bit TMA3 in TMA. For details, see table 5.2. 2 MSON 0 R/W Medium Speed on Flag After standby, watch, or sleep mode is cleared, this bit selects active (high-speed) or active (medium-speed) mode. 0: Operation in active (high-speed) mode 1: Operation in active (medium-speed) mode 1 0 SA1 SA0 0 0 R/W R/W Subactive Mode Clock Select 1 and 0 Select the operating clock frequency in subactive and subsleep modes. The operating clock frequency changes to the set frequency after the SLEEP instruction is executed. 00: W/8 01: W/4 1x: W/2 [Legend] x: Don't care. Rev. 1.00 Dec. 13, 2007 Page 90 of 380 REJ09B0430-0100 Section 5 Power-Down Modes 5.1.3 Clock Halt Registers 1 and 2 (CKSTPR1 and CKSTPR2) CKSTPR1 and CKSTPR2 allow the on-chip peripheral modules to enter a standby state in module units. * CKSTPR1 Bit 7, 6 5 Bit Name S32CKSTP Initial Value All 1 1 R/W R/W Description Reserved SCI Module Standby SCI3 enters standby mode when this bit is cleared to 1 0.* 4 ADCKSTP 1 R/W A/D Converter Module Standby A/D converter enters standby mode when this bit is cleared to 0. 3 2 TFCKSTP 1 1 R/W Reserved Timer F Module Standby Timer F enters standby mode when this bit is cleared to 0. 1 0 TACKSTP 1 1 R/W Reserved Timer A Module Standby*2 Timer A enters standby mode when this bit is cleared to 0. Rev. 1.00 Dec. 13, 2007 Page 91 of 380 REJ09B0430-0100 Section 5 Power-Down Modes * CKSTPR2 Bit 7 6, 5 4 Bit Name Initial Value 1 All 1 R/W R/W R/W* 3 Description Reserved Reserved PWM2 Module Standby PWM2 enters standby mode when this bit is cleared to 0. PW2CKSTP 1 3 AECKSTP 1 R/W Asynchronous Event Counter Module Standby Asynchronous event counter enters standby mode when this bit is cleared to 0 2 WDCKSTP 1 R/W*4 Watchdog Timer Module Standby Watchdog timer enters standby mode when this bit is cleared to 0 1 PW1CKSTP 1 R/W PWM1 Module Standby PWM1 enters standby mode when this bit is cleared to 0 0 1 Reserved Notes: 1. When the SCI module standby is set, all registers in the SCI3 enter the reset state. 2. When the timer A module standby is set, the TMA3 bit in TMA cannot be rewritten. When the TMA3 bit is rewritten, the TACKSTP bit in CKSTPR1 should be set to 1 in advance. 5.2 Mode Transitions and States of LSI Figure 5.1 shows the possible transitions among these operating modes. A transition is made from the program execution state to the program halt state of the program by executing a SLEEP instruction. Interrupts allow for returning from the program halt state to the program execution state of the program. A direct transition between active mode and subactive mode, which are both program execution states, can be made without halting the program. The operating frequency can also be changed in the same modes by making a transition directly from active mode to active mode, and from subactive mode to subactive mode. RES input enables transitions from a mode to the reset state. Table 5.2 shows the transition conditions of each mode after the SLEEP instruction is executed and a mode to return by an interrupt. Table 5.3 shows the internal states of the LSI in each mode. Rev. 1.00 Dec. 13, 2007 Page 92 of 380 REJ09B0430-0100 Section 5 Power-Down Modes Reset state Program halt state Standby mode SLEEP d instruction 4 d SLEEP instruction Program execution state Active (high-speed mode) g f SLEEP instruction 4 SLEEP instruction SLEEP instruction a 3 a EP ion Et SL truc s in Pn EE tio SL truc s in Program halt state Sleep (high-speed) mode b SLEEP b instruction e SLEEP instruction 1 e S ins LE tru EP cti on Active (medium-speed) mode j SLEEP instruction i h SLEEP instruction SLEEP instruction i SLEEP instruction 3 Sleep (medium-speed) mode 1 Watch mode e SLEEP instruction 1 Subactive mode SLEEP instruction c Subsleep 2 mode : Transition is made after exception handling is executed. Mode Transition Conditions (1) LSON a b c d e f g h i j 0 0 1 0 * 0 0 0 1 0 MSON SSBY 0 1 * * * 0 1 1 * 0 0 0 0 1 1 0 0 1 1 1 TMA3 * * 1 0 1 * * 1 1 1 DTON 0 0 0 0 0 1 1 1 1 1 3 4 2 1 Power-down modes Mode Transition Conditions (2) Interrupt Sources Timer A, Timer F, IRQ0 interrupt, WKP7 to WKP0 interrupts Timer A, Timer F, SCI3 interrupt, IRQ1 and IRQ0, IRQAEC interrupts, WKP7 o WKP0 interrupts, AEC All interrupts IRQ1 or IRQ0, WKP7 to WKP0 interrupts [Legend] * Don't care Note: A transition between different modes cannot be made to occur simply because an interrupt request is generated. Make sure that interrupts are enabled. Figure 5.1 Mode Transition Diagram Rev. 1.00 Dec. 13, 2007 Page 93 of 380 REJ09B0430-0100 Section 5 Power-Down Modes Table 5.2 Transition Mode after SLEEP Instruction Execution and Interrupt Handling Transition Mode after SLEEP Transition State Before Instruction Mode due to Transition LSON MSON SSBY TMA3 DTON Execution Interrupt Active (highspeed) mode 0 0 0 x 0 Sleep (highspeed) mode Sleep (mediumspeed) mode Standby mode Standby mode Watch mode Watch mode Watch mode Active (highspeed) mode (direct transition) Active (mediumspeed) mode (direct transition) Subactive mode (direct transition) Active (highspeed) mode Symbol in Figure 5.1 a 0 1 0 x 0 Active (mediumspeed) mode Active (highspeed) mode Active (mediumspeed) mode Active (highspeed) mode Active (mediumspeed) mode b 0 0 0 1 1 1 0 0 0 0 d d 0 0 0 1 1 1 1 1 0 0 e e 1 0 x 0 1 0 1 x 0 1 Subactive mode e 0 1 0 x 1 g 1 x 1 1 1 i Rev. 1.00 Dec. 13, 2007 Page 94 of 380 REJ09B0430-0100 Section 5 Power-Down Modes Transition Mode after SLEEP Transition State Before Instruction Mode due to Transition LSON MSON SSBY TMA3 DTON Execution Interrupt Active (mediumspeed) mode 0 0 0 x 0 Sleep (highspeed) mode Sleep (mediumspeed) mode Standby mode Standby mode Watch mode Watch mode Watch mode Active (highspeed) mode (direct transition) Active (mediumspeed) mode (direct transition) Subactive mode (direct transition) Active (highspeed) mode Symbol in Figure 6.1 a 0 1 0 x 0 Active (mediumspeed) mode Active (highspeed) mode Active (mediumspeed) mode Active (highspeed) mode Active (mediumspeed) mode b 0 0 0 1 1 1 0 0 0 0 d d 0 0 0 1 1 1 1 1 0 0 e e 1 0 1 0 1 0 1 x 0 1 Subactive mode e f 0 1 0 x 1 1 x 1 1 1 i Rev. 1.00 Dec. 13, 2007 Page 95 of 380 REJ09B0430-0100 Section 5 Power-Down Modes Transition Mode after SLEEP Transition State Before Instruction Mode due to Transition LSON MSON SSBY TMA3 DTON Execution Interrupt Subactive mode 1 0 0 x 0 1 0 1 1 1 1 1 0 0 0 Subsleep mode Watch mode Watch mode Watch mode Active (highspeed) mode (direct transition) Active (mediumspeed) mode (direct transition) Subactive mode (direct transition) Symbol in Figure 6.1 Subactive mode c Active (highspeed) mode Active (mediumspeed) mode e e 1 0 x 0 1 1 1 1 0 1 Subactive mode e j 0 1 1 1 1 h 1 x 1 1 1 [Legend] x: Don't care Rev. 1.00 Dec. 13, 2007 Page 96 of 380 REJ09B0430-0100 Section 5 Power-Down Modes Table 5.3 Internal State in Each Operating Mode Active Mode High-speed Mediumspeed Functioning Functioning Functioning Functioning Functioning Functioning Functioning Functioning Halted Retained Sleep Mode High-speed Mediumspeed Functioning Functioning Halted Retained Subactive Watch Mode Mode Halted Functioning Halted Retained Halted Functioning Functioning Subsleep Mode Halted Functioning Halted Retained Stand-by Mode Halted Functioning Halted Retained Function System clock oscillator Subclock oscillator CPU Instructions RAM Registers I/O External interrupts IRQ0 IRQ1 IRQAEC WKP7 to WKP0 Peripheral modules Timer A Asynchronous counter Timer F Functioning Functioning Retained*1 Functioning Functioning Functioning Functioning Retained*4 Retained* Functioning 4 Functioning Functioning Functioning Functioning Functioning Functioning Functioning Functioning*3 Functioning*3 Functioning*3 Retained Functioning*5 Functioning Functioning Functioning*5 Functioning/ retained*6 Functioning/ retained*6 Functioning/ retained*7 Functioning/ retained*6*7 Functioning/ retained*8 Retained WDT Functioning/ retained*8 Functioning/ retained*8 Reset SCI3 Functioning Functioning Functioning Functioning Reset retained*2 PWM Peripheral modules A/D converter Functioning Functioning Functioning Functioning Functioning Functioning Functioning Functioning Retained Retained Retained Retained Functioning/| Functioning/ retained*2 Retained Retained Retained Retained Notes: 1. 2. 3. 4. 5. 6. 7. 8. Register contents are retained. Output is the high-impedance state. Functioning if W/2 is selected as an internal clock, or halted and retained otherwise. Functioning if the timekeeping time-base function is selected. An external interrupt request is ignored. Contents of the interrupt request register are not affected. The counter can be incremented. An interrupt cannot occur. Functioning if w/4 is selected as an internal clock. Halted and retained otherwise. Operates when w/32 is selected as the internal clock; otherwise stops and stands by. Stops and stands by. Rev. 1.00 Dec. 13, 2007 Page 97 of 380 REJ09B0430-0100 Section 5 Power-Down Modes 5.2.1 Sleep Mode In sleep mode, CPU operation is halted but the system clock oscillator, subclock oscillator, and on-chip peripheral modules function. In sleep (medium-speed) mode, the on-chip peripheral modules function at the clock frequency set by the MA1 and MA0 bits in SYSCR1. CPU register contents are retained. Sleep mode is cleared by an interrupt. When an interrupt is requested, sleep mode is cleared and interrupt exception handling starts. Sleep mode is not cleared if the I bit in CCR is set to 1 or the requested interrupt is disabled by the interrupt enable bit. After sleep mode is cleared, a transition is made from sleep (high-speed) mode to active (high-speed) mode or from sleep (medium-speed) mode to active (medium-speed) mode. When the RES pin goes low, the CPU goes into the reset state and sleep mode is cleared. Since an interrupt request signal is synchronous with the system clock, the maximum time of 2/ (s) may be delayed from the point at which an interrupt request signal occurs until the interrupt exception handling is started. Furthermore, it sometimes operates with half state early timing at the time of transition to sleep (medium-speed) mode. Rev. 1.00 Dec. 13, 2007 Page 98 of 380 REJ09B0430-0100 Section 5 Power-Down Modes 5.2.2 Standby Mode In standby mode, the clock pulse generator stops, so the CPU and on-chip peripheral modules stop functioning. However, as long as the rated voltage is supplied, the contents of CPU registers, onchip RAM, and some on-chip peripheral module registers are retained. On-chip RAM contents will be retained as long as the voltage set by the RAM data retention voltage is provided. The I/O ports go to the high-impedance state. Standby mode is cleared by an interrupt. When an interrupt is requested, the system clock pulse generator starts. After the time set in bits STS2 to STS0 in SYSCR1 has elapsed, standby mode is cleared and interrupt exception handling starts. After standby mode is cleared, a transition is made to active (high-speed) or active (medium-speed) mode according to the MSON bit in SYSCR2. Standby mode is not cleared if the I bit in CCR is set to 1 or the requested interrupt is disabled by the interrupt enable bit. When the RES pin goes low, the system clock pulse generator starts. Since system clock signals are supplied to the entire chip as soon as the system clock pulse generator starts functioning, the RES pin must be kept low until the pulse generator output stabilizes. After the pulse generator output has stabilized, the CPU starts reset exception handling if the RES pin is driven high. 5.2.3 Watch Mode In watch mode, the system clock oscillator and CPU operation stop and on-chip peripheral modules stop functioning except for the timer A, timer F, and asynchronous event counter. However, as long as the rated voltage is supplied, the contents of CPU registers, some on-chip peripheral module registers, and on-chip RAM are retained. The I/O ports retain their state before the transition. Watch mode is cleared by an interrupt. When an interrupt is requested, watch mode is cleared and interrupt exception handling starts. When watch mode is cleared by an interrupt, a transition is made to active (high-speed) mode, active (medium-speed) mode, or subactive mode depending on the settings of the LSON bit in SYSCR1 and the MSON bit in SYSCR2. When the transition is made to active mode, after the time set in bits STS2 to STS0 in SYSCR1 has elapsed, interrupt exception handling starts. Watch mode is not cleared if the I bit in CCR is set to 1 or the requested interrupt is disabled by the interrupt enable bit. When the RES pin goes low, the system clock pulse generator starts. Since system clock signals are supplied to the entire chip as soon as the system clock pulse generator starts functioning, the RES pin must be kept low until the pulse generator output stabilizes. After the pulse generator output has stabilized, the CPU starts reset exception handling if the RES pin is driven high. Rev. 1.00 Dec. 13, 2007 Page 99 of 380 REJ09B0430-0100 Section 5 Power-Down Modes 5.2.4 Subsleep Mode In subsleep mode, the CPU operation stops but on-chip peripheral modules other than the A/D converter and PWM function. As long as a required voltage is applied, the contents of CPU registers, the on-chip RAM, and some registers of the on-chip peripheral modules are retained. I/O ports keep the same states as before the transition. Subsleep mode is cleared by an interrupt. When an interrupt is requested, subsleep mode is cleared and interrupt exception handling starts. After subsleep mode is cleared, a transition is made to subactive mode. Subsleep mode is not cleared if the I bit in CCR is set to 1 or the requested interrupt is disabled in the interrupt enable register. When the RES pin goes low, the system clock pulse generator starts. Since system clock signals are supplied to the entire chip as soon as the system clock pulse generator starts functioning, the RES pin must be kept low until the pulse generator output stabilizes. After the pulse generator output has stabilized, the CPU starts reset exception handling if the RES pin is driven high. 5.2.5 Subactive Mode In subactive mode, the system clock oscillator stops but on-chip peripheral modules other than the A/D converter and PWM function. As long as a required voltage is applied, the contents of some registers of the on-chip peripheral modules are retained. Subactive mode is cleared by the SLEEP instruction. When subacitve mode is cleared, a transition to subsleep mode, active mode, or watch mode is made, depending on the combination of bits SSBY and LSON in SYSCR1, bits MSON and DTON in SYSCR2, and bit TMA3 in TMA. Subactive mode is not cleared if the I bit in CCR is set to 1 or the requested interrupt is disabled in the interrupt enable register. When the RES pin goes low, the system clock pulse generator starts. Since system clock signals are supplied to the entire chip as soon as the system clock pulse generator starts functioning, the RES pin must be kept low until the pulse generator output stabilizes. After the pulse generator output has stabilized, the CPU starts reset exception handling if the RES pin is driven high. The operating frequency of subactive mode is selected from W/2, W/4, and W/8 by the SA1 and SA0 bits in SYSCR2. After the SLEEP instruction is executed, the operating frequency changes to the frequency which is set before the execution. Rev. 1.00 Dec. 13, 2007 Page 100 of 380 REJ09B0430-0100 Section 5 Power-Down Modes 5.2.6 Active (Medium-Speed) Mode In active (medium-speed) mode, the system clock oscillator, subclock oscillator, CPU, and onchip peripheral modules function. Active (medium-speed) mode is cleared by the SLEEP instruction. When active (medium-speed) mode is cleared, a transition to standby mode is made depending on the combination of bits SSBY and LSON in SYSCR1 and bit TMA3 in TMA, a transition to watch mode is made depending on the combination of bit SSBY in SYSCR1 and bit TMA3 in TMA, or a transition to sleep mode is made depending on the combination of bits SSBY and LSON in SYSCR1. Moreover, a transition to active (high-speed) mode or subactive mode is made by a direct transition. Active (mediumsleep) mode is not entered if the I bit in CCR is set to 1 or the requested interrupt is disabled in the interrupt enable register. When the RES pin goes low, the CPU goes into the reset state and active (medium-sleep) mode is cleared. Furthermore, it sometimes operates with half state early timing at the time of transition to active (medium-speed) mode. In active (medium-speed) mode, the on-chip peripheral modules function at the clock frequency set by the MA1 and MA0 bits in SYSCR1. Rev. 1.00 Dec. 13, 2007 Page 101 of 380 REJ09B0430-0100 Section 5 Power-Down Modes 5.3 Direct Transition The CPU can execute programs in two modes: active and subactive mode. A direct transition is a transition between these two modes without stopping program execution. A direct transition can be made by executing a SLEEP instruction while the DTON bit in SYSCR2 is set to 1. The direct transition also enables operating frequency modification in active or subactive mode. After the mode transition, direct transition interrupt exception handling starts. If the direct transition interrupt is disabled in interrupt permission register 2, a transition is made instead to sleep or watch mode. Note that if a direct transition is attempted while the I bit in CCR is set to 1, sleep or watch mode will be entered, and the resulting mode cannot be cleared by means of an interrupt. * Direct transfer from active (high-speed) mode to active (medium-speed) mode When a SLEEP instruction is executed in active (high-speed) mode while the SSBY and LSON bits in SYSCR1 are cleared to 0, the MSON bit in SYSCR2 is set to 1, and the DTON bit in SYSCR2 is set to 1, a transition is made to active (medium-speed) mode via sleep mode. * Direct transfer from active (medium-speed) mode to active (high-speed) mode When a SLEEP instruction is executed in active (medium-speed) mode while the SSBY and LSON bits in SYSCR1 are cleared to 0, the MSON bit in SYSCR2 is cleared to 0, and the DTON bit in SYSCR2 is set to 1, a transition is made to active (high-speed) mode via sleep mode. * Direct transfer from active (high-speed) mode to subactive mode When a SLEEP instruction is executed in active (high-speed) mode while the SSBY and LSON bits in SYSCR1 are set to 1, the DTON bit in SYSCR2 is set to 1, and the TMA3 bit in TMA is set to 1, a transition is made to subactive mode via watch mode. * Direct transfer from subactive mode to active (high-speed) mode When a SLEEP instruction is executed in subactive mode while the SSBY bit in SYSCR1 is set to 1, the LSON bit in SYSCR1 is cleared to 0, the MSON bit in SYSCR2 is cleared to 0, the DTON bit in SYSCR2 is set to 1, and the TMA3 bit in TMA is set to 1, a transition is made directly to active (high-speed) mode via watch mode after the waiting time set in bits STS2 to STS0 in SYSCR1 has elapsed. * Direct transfer from active (medium-speed) mode to subactive mode When a SLEEP instruction is executed in active (medium-speed) while the SSBY and LSON bits in SYSCR1 are set to 1, the DTON bit in SYSCR2 is set to 1, and the TMA3 bit in TMA is set to 1, a transition is made to subactive mode via watch mode. Rev. 1.00 Dec. 13, 2007 Page 102 of 380 REJ09B0430-0100 Section 5 Power-Down Modes * Direct transfer from subactive mode to active (medium-speed) mode When a SLEEP instruction is executed in subactive mode while the SSBY bit in SYSCR1 is set to 1, the LSON bit in SYSCR1 is cleared to 0, the MSON bit in SYSCR2 is set to 1, the DTON bit in SYSCR2 is set to 1, and the TMA3 bit in TMA is set to 1, a transition is made directly to active (medium-speed) mode via watch mode after the waiting time set in bits STS2 to STS0 in SYSCR1 has elapsed. 5.3.1 Direct Transition from Active (High-Speed) Mode to Active (Medium-Speed) Mode The time from the start of SLEEP instruction execution to the end of interrupt exception handling (the direct transition time) is calculated by equation (1). Direct transition time = {(Number of SLEEP instruction execution states) + (Number of internal processing states)} x (tcyc before transition) + (Number of interrupt exception handling execution states) x (tcyc after transition) .....................(1) Example: Direct transition time = (2 + 1) x 2tosc + 14 x 16tosc = 230tosc (when /8 is selected as the CPU operating clock) Legend: tosc: OSC clock cycle time tcyc: System clock () cycle time Rev. 1.00 Dec. 13, 2007 Page 103 of 380 REJ09B0430-0100 Section 5 Power-Down Modes 5.3.2 Direct Transition from Active (Medium-Speed) Mode to Active (High-Speed) Mode The time from the start of SLEEP instruction execution to the end of interrupt exception handling (the direct transition time) is calculated by equation (2). Direct transition time = {(Number of SLEEP instruction execution states) + (Number of internal processing states)} x (tcyc before transition) + (Number of interrupt exception handling execution states) x (tcyc after transition) ....................(2) Example: Direct transition time = (2 + 1) x 16tosc + 14 x 2tosc = 76tosc (when /8 is selected as the CPU operating clock) Legend: tosc: OSC clock cycle time tcyc: System clock () cycle time 5.3.3 Direct Transition from Subactive Mode to Active (High-Speed) Mode The time from the start of SLEEP instruction execution to the end of interrupt exception handling (the direct transition time) is calculated by equation (3). Direct transition time = {(Number of SLEEP instruction execution states) + (Number of internal processing states)} x (tsubcyc before transition) + {(Wait time set in bits STS2 to STS0) + (Number of interrupt exception handling execution states)} x (tcyc after transition) ....................(3) Example: Direct transition time = (2 + 1) x 8tw + (8192 + 14) x 2tosc = 24tw + 16412tosc (when w/8 is selected as the CPU operating clock and wait time = 8192 states) Legend: tosc: tw: tcyc: tsubcyc: OSC clock cycle time Watch clock cycle time System clock () cycle time Subclock (SUB) cycle time Rev. 1.00 Dec. 13, 2007 Page 104 of 380 REJ09B0430-0100 Section 5 Power-Down Modes 5.3.4 Direct Transition from Subactive Mode to Active (Medium-Speed) Mode The time from the start of SLEEP instruction execution to the end of interrupt exception handling (the direct transition time) is calculated by equation (4). Direct transition time = {(Number of SLEEP instruction execution states) + (Number of internal processing states)} x (tsubcyc before transition) + {(Wait time set in bits STS2 to STS0) + (Number of interrupt exception handling execution states)} x (tcyc after transition) ....................(4) Example: Direct transition time = (2 + 1) x 8tw + (8192 + 14) x 16tosc = 24tw + 131296tosc (when w/8 or /8 is selected as the CPU operating clock and wait time = 8192 states) Legend: tosc: tw: tcyc: tsubcyc: 5.3.5 OSC clock cycle time Watch clock cycle time System clock () cycle time Subclock (SUB) cycle time Notes on External Input Signal Changes before/after Direct Transition * Direct transition from active (high-speed) mode to subactive mode Since the mode transition is performed via watch mode, see section 5.5.2, Notes on External Input Signal Changes before/after Standby Mode. * Direct transition from active (medium-speed) mode to subactive mode Since the mode transition is performed via watch mode, see section 5.5.2, Notes on External Input Signal Changes before/after Standby Mode. * Direct transition from subactive mode to active (high-speed) mode Since the mode transition is performed via watch mode, see section 5.5.2, Notes on External Input Signal Changes before/after Standby Mode. * Direct transition from subactive mode to active (medium-speed) mode Since the mode transition is performed via watch mode, see section 5.5.2, Notes on External Input Signal Changes before/after Standby Mode. Rev. 1.00 Dec. 13, 2007 Page 105 of 380 REJ09B0430-0100 Section 5 Power-Down Modes 5.4 Module Standby Function The module-standby function can be set to any peripheral module. In module standby mode, the clock supply to modules stops to enter the power-down mode. Module standby mode enables each on-chip peripheral module to enter the standby state by clearing a bit that corresponds to each module in CKSTPR1 and CKSTPR2 to 0 and cancels the mode by setting the bit to 1. (See section 5.1.3, Clock Halt Registers 1 and 2 (CKSTPR1 and CKSTPR2).) 5.5 5.5.1 Usage Notes Standby Mode Transition and Pin States When a SLEEP instruction is executed in active (high-speed) mode or active (medium-speed) mode while bit SSBY is set to 1 and bit LSON is cleared to 0 in SYSCR1, and bit TMA3 is cleared to 0 in TMA, a transition is made to standby mode. At the same time, pins go to the highimpedance state (except pins for which the pull-up MOS is designated as on). Figure 5.2 shows the timing in this case. Internal data bus SLEEP instruction fetch Next instruction fetch Internal processing High-impedance Standby mode SLEEP instruction execution Pins Port output Active (high-speed) mode or active (medium-speed) mode Figure 5.2 Standby Mode Transition and Pin States Rev. 1.00 Dec. 13, 2007 Page 106 of 380 REJ09B0430-0100 Section 5 Power-Down Modes 5.5.2 Notes on External Input Signal Changes before/after Standby Mode 1. When external input signal changes before/after standby mode or watch mode When an external input signal such as IRQ, WKP, or IRQAEC is input, both the high- and low-level widths of the signal must be at least two cycles of system clock or subclock SUB (referred to together in this section as the internal clock). As the internal clock stops in standby mode and watch mode, the width of external input signals requires careful attention when a transition is made via these operating modes. Ensure that external input signals conform to the conditions stated in 3, Recommended timing of external input signals, below. 2. When external input signals cannot be captured because internal clock stops The case of falling edge capture is shown in figure 5.3. As shown in the case marked "Capture not possible," when an external input signal falls immediately after a transition to active (high-speed or medium-speed) mode or subactive mode, after oscillation is started by an interrupt via a different signal, the external input signal cannot be captured if the high-level width at that point is less than 2 tcyc or 2 tsubcyc. 3. Recommended timing of external input signals To ensure dependable capture of an external input signal, high- and low-level signal widths of at least 2 tcyc or 2 tsubcyc are necessary before a transition is made to standby mode or watch mode, as shown in "Capture possible: case 1." External input signal capture is also possible with the timing shown in "Capture possible: case 2" and "Capture possible: case 3," in which a 2 tcyc or 2 tsubcyc level width is secured. Wait for oscillation stabilization Operating mode Active (high-speed, medium-speed) mode or subactive mode tcyc tsubcyc tcyc tsubcyc Standby mode or watch mode tcyc tsubcyc Active (high-speed, medium-speed) mode or subactive mode tcyc tsubcyc or SUB External input signal Capture possible: case 1 Capture possible: case 2 Capture possible: case 3 Capture not possible Interrupt by different signal Figure 5.3 External Input Signal Capture when Signal Changes before/after Standby Mode or Watch Mode Rev. 1.00 Dec. 13, 2007 Page 107 of 380 REJ09B0430-0100 Section 5 Power-Down Modes 4. Input pins to which these notes apply: IRQ1, IRQ0, WKP7 to WKP0, and IRQAEC Rev. 1.00 Dec. 13, 2007 Page 108 of 380 REJ09B0430-0100 Section 6 ROM Section 6 ROM The H8/38704 has 32 kbytes of the on-chip mask ROM, the H8/38703 has 24 kbytes, the H8/38702 and H8/38702S have 16 kbytes, the H8/38701S has 12 kbytes, and the H8/38700S has 8 kbytes. The ROM is connected to the CPU by a 16-bit data bus, allowing high-speed two-state access for both byte data and word data. The H8/38704 and H8/38702 have flash ROM versions with 32-kbyte flash memory and 16-kbyte flash memory, respectively. 6.1 Block Diagram Figure 6.1 shows a block diagram of the on-chip ROM. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) H'0000 H'0002 H'0000 H'0002 H'0001 H'0003 On-chip ROM H'7FFE H'7FFE Even address H'7FFF Odd address Figure 6.1 Block Diagram of ROM Rev. 1.00 Dec. 13, 2007 Page 109 of 380 REJ09B0430-0100 Section 6 ROM 6.2 6.2.1 Overview of Flash Memory Features The features of the 32-kbyte or 16-kbyte flash memory built into the flash memory version are summarized below. * Programming/erase methods The flash memory is programmed 128 bytes at a time. Erase is performed in single-block units. The 32-kbyte flash memory are configured as 1 kbyte x 4 blocks and 28 kbytes x 1 block. The 16-kbyte flash memory is configured as 1 kbyte x 4 blocks and 12 kbytes x 1 block. To erase the entire flash memory, each block must be erased in turn. * On-board programming On-board programming/erasing can be done in boot mode, in which the boot program built into the chip is started to erase or program of the entire flash memory. In normal user program mode, individual blocks can be erased or programmed. * Programmer mode Flash memory can be programmed/erased in programmer mode using a PROM programmer, as well as in on-board programming mode. * Automatic bit rate adjustment For data transfer in boot mode, this LSI's bit rate can be automatically adjusted to match the transfer bit rate of the host. * Programming/erasing protection Sets software protection against flash memory programming/erasing. * Power-down mode Operation of the power supply circuit can be partly halted in subactive mode. As a result, flash memory can be read with low power consumption. Rev. 1.00 Dec. 13, 2007 Page 110 of 380 REJ09B0430-0100 Section 6 ROM 6.2.2 Block Diagram Internal address bus Internal data bus (16 bits) FLMCR1 FLMCR2 Module bus Bus interface/controller EBR FLPWCR FENR Operating mode TEST pin P95 pin P34 pin Flash memory [Legend] FLMCR1: FLMCR2: EBR: FLPWCR: FENR: Flash memory control register 1 Flash memory control register 2 Erase block register Flash memory power control register Flash memory enable register Figure 6.2 Block Diagram of Flash Memory Rev. 1.00 Dec. 13, 2007 Page 111 of 380 REJ09B0430-0100 Section 6 ROM 6.2.3 Block Configuration Figure 6.3 shows the block configuration of 32-kbyte flash memory. The thick lines indicate erasing units, the narrow lines indicate programming units, and the values are addresses. The 32kbyte flash memory is divided into 1 kbyte x 4 blocks and 28 kbytes x 1 block. Erasing is performed in these units. The 16-kbyte flash memory is divided into 1 kbyte x 4 blocks and 12 kbytes x 1 block. Programming is performed in 128-byte units starting from an address with lower eight bits H'00 or H'80. H'0000 Erase unit 1 kbyte H'0380 H'0400 Erase unit 1 kbyte H'0780 H'0800 Erase unit 1 kbyte H'0B80 H'0C00 Erase unit 1 kbyte H'0F80 H'1000 Erase unit 28 kbytes H'1080 H'0C80 H'0880 H'0480 H'0080 H'0001 H'0081 H'0002 H'0082 Programming unit: 128 bytes H'007F H'00FF H'0381 H'0401 H'0481 H'0382 H'0402 H'0482 Programming unit: 128 bytes H'03FF H'047F H'04FF H'0781 H'0801 H'0881 H'0782 H'0802 H'0882 Programming unit: 128 bytes H'07FF H'087F H'08FF H'0B81 H'0C01 H'0C81 H'0B82 H'0C02 H'0C82 Programming unit: 128 bytes H'0BFF H'0C7F H'0CFF H'0F81 H'1001 H'1081 H'0F82 H'1002 H'1082 Programming unit: 128 bytes H'0FFF H'107F H'10FF H'7F80 H'7F81 H'7F82 H'7FFF Figure 6.3(1) Block Configuration of 32-kbyte Flash Memory Rev. 1.00 Dec. 13, 2007 Page 112 of 380 REJ09B0430-0100 Section 6 ROM H'0000 Erase unit 1 kbyte H'0380 H'0400 Erase unit 1 kbyte H'0780 H'0800 Erase unit 1 kbyte H'0B80 H'0C00 Erase unit 1 kbyte H'0F80 H'1000 Erase unit 12 kbytes H'1080 H'0C80 H'0880 H'0480 H'0080 H'0001 H'0081 H'0002 H'0082 Programming unit: 128 bytes H'007F H'00FF H'0381 H'0401 H'0481 H'0382 H'0402 H'0482 Programming unit: 128 bytes H'03FF H'047F H'04FF H'0781 H'0801 H'0881 H'0782 H'0802 H'0882 Programming unit: 128 bytes H'07FF H'087F H'08FF H'0B81 H'0C01 H'0C81 H'0B82 H'0C02 H'0C82 Programming unit: 128 bytes H'0BFF H'0C7F H'0CFF H'0F81 H'1001 H'1081 H'0F82 H'1002 H'1082 Programming unit: 128 bytes H'0FFF H'107F H'10FF H'3F80 H'3F81 H'3F82 H'3FFF Figure 6.3(2) Block Configuration of 16-kbyte Flash Memory 6.3 Register Descriptions The flash memory has the following registers. * * * * * Flash memory control register 1 (FLMCR1) Flash memory control register 2 (FLMCR2) Erase block register (EBR) Flash memory power control register (FLPWCR) Flash memory enable register (FENR) Rev. 1.00 Dec. 13, 2007 Page 113 of 380 REJ09B0430-0100 Section 6 ROM 6.3.1 Flash Memory Control Register 1 (FLMCR1) FLMCR1 is a register that makes the flash memory change to program mode, program-verify mode, erase mode, or erase-verify mode. For details on register setting, refer to section 6.5, Flash Memory Programming/Erasing. Bit 7 Bit Name -- Initial Value 0 R/W -- Description Reserved This bit is always read as 0. 6 SWE 0 R/W Software Write Enable When this bit is set to 1, flash memory programming/erasing is enabled. When this bit is cleared to 0, flash memory programming/erasing is invalid. Other FLMCR1 bits and all EBR bits cannot be set. 5 ESU 0 R/W Erase Setup When this bit is set to 1, the flash memory changes to the erase setup state. When it is cleared to 0, the erase setup state is cancelled. Set this bit to 1 before setting the E bit to 1 in FLMCR1. 4 PSU 0 R/W Program Setup When this bit is set to 1, the flash memory changes to the program setup state. When it is cleared to 0, the program setup state is cancelled. Set this bit to 1 before setting the P bit in FLMCR1. 3 EV 0 R/W Erase-Verify When this bit is set to 1, the flash memory changes to erase-verify mode. When it is cleared to 0, erase-verify mode is cancelled. 2 PV 0 R/W Program-Verify When this bit is set to 1, the flash memory changes to program-verify mode. When it is cleared to 0, programverify mode is cancelled. 1 E 0 R/W Erase When this bit is set to 1, and while the SWE = 1 and ESU = 1 bits are 1, the flash memory changes to erase mode. When it is cleared to 0, erase mode is cancelled. 0 P 0 R/W Program When this bit is set to 1, and while the SWE = 1 and PSU = 1 bits are 1, the flash memory changes to program mode. When it is cleared to 0, program mode is cancelled. Note: Bits SWE, PSU, EV, PV, E, and P should not be set at the same time. Rev. 1.00 Dec. 13, 2007 Page 114 of 380 REJ09B0430-0100 Section 6 ROM 6.3.2 Flash Memory Control Register 2 (FLMCR2) FLMCR2 is a register that displays the state of flash memory programming/erasing. FLMCR2 is a read-only register, and should not be written to. Bit 7 Bit Name FLER Initial Value 0 R/W R Description Flash Memory Error Indicates that an error has occurred during an operation on flash memory (programming or erasing). When flash memory goes to the error-protection state, this bit is set to 1. See section 6.6.3, Error Protection, for details. 6 to 0 -- All 0 -- Reserved These bits are always read as 0. 6.3.3 Erase Block Register (EBR) EBR specifies the flash memory erase area block. EBR is initialized to H'00 when the SWE bit in FLMCR1 is 0. Do not set more than one bit at a time, as this will cause all the bits in EBR to be automatically cleared to 0. Bit 7 to 5 4 Bit Name -- EB4 Initial Value All 0 0 R/W -- R/W Description Reserved These bits are always read as 0. H8/38704F: When this bit is set to 1, 28 kbytes of H'1000 to H'7FFF will be erased. H8/38702F: When this bit is set to 1, 12 kbytes of H'1000 to H'3FFF will be erased. 3 2 1 0 EB3 EB2 EB1 EB0 0 0 0 0 R/W R/W R/W R/W When this bit is set to 1, 1 kbyte of H'0C00 to H'0FFF will be erased. When this bit is set to 1, 1 kbyte of H'0800 to H'0BFF will be erased. When this bit is set to 1, 1 kbyte of H'0400 to H'07FF will be erased. When this bit is set to 1, 1 kbyte of H'0000 to H'03FF will be erased. Rev. 1.00 Dec. 13, 2007 Page 115 of 380 REJ09B0430-0100 Section 6 ROM 6.3.4 Flash Memory Power Control Register (FLPWCR) FLPWCR enables or disables a transition to the flash memory power-down mode when the LSI switches to subactive mode. There are two modes: mode in which operation of the power supply circuit of flash memory is partly halted in power-down mode and flash memory can be read, and mode in which even if a transition is made to subactive mode, operation of the power supply circuit of flash memory is retained and flash memory can be read. Bit 7 Bit Name PDWND Initial Value 0 R/W R/W Description Power-Down Disable When this bit is 0 and a transition is made to subactive mode, the flash memory enters the power-down mode. When this bit is 1, the flash memory remains in the normal mode even after a transition is made to subactive mode. 6 to 0 -- All 0 -- Reserved These bits are always read as 0. 6.3.5 Flash Memory Enable Register (FENR) Bit 7 (FLSHE) in FENR enables or disables the CPU access to the flash memory control registers, FLMCR1, FLMCR2, EBR, and FLPWCR. Bit 7 Bit Name FLSHE Initial Value 0 R/W R/W Description Flash Memory Control Register Enable Flash memory control registers can be accessed when this bit is set to 1. Flash memory control registers cannot be accessed when this bit is set to 0. 6 to 0 -- All 0 -- Reserved These bits are always read as 0. Rev. 1.00 Dec. 13, 2007 Page 116 of 380 REJ09B0430-0100 Section 6 ROM 6.4 On-Board Programming Modes There are two modes for programming/erasing of the flash memory; boot mode, which enables onboard programming/erasing, and programmer mode, in which programming/erasing is performed with a PROM programmer. On-board programming/erasing can also be performed in user program mode. At reset-start in reset mode, this LSI changes to a mode depending on the TEST pin settings, P95 pin settings, and input level of each port, as shown in table 6.1. The input level of each pin must be defined four states before the reset ends. When changing to boot mode, the boot program built into this LSI is initiated. The boot program transfers the programming control program from the externally-connected host to on-chip RAM via SCI3. After erasing the entire flash memory, the programming control program is executed. This can be used for programming initial values in the on-board state or for a forcible return when programming/erasing can no longer be done in user program mode. In user program mode, individual blocks can be erased and programmed by branching to the user program/erase control program prepared by the user. Table 6.1 TEST 0 0 1 Setting Programming Modes P95 1 0 x P34 x 1 x PB0 x x 0 PB1 x x 0 PB2 x x 0 LSI State after Reset End User Mode Boot Mode Programmer Mode [Legend] x: Don't care. 6.4.1 Boot Mode Table 6.2 shows the boot mode operations between reset end and branching to the programming control program. 1. When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. Prepare a programming control program in accordance with the description in section 6.5, Flash Memory Programming/Erasing. 2. The SCI3 should be set to asynchronous mode, and the transfer format as follows: 8-bit data, 1 stop bit, and no parity. Since the inversion function of SPCR is configured not to inverse data of the TXD pin and RXD pin, do not place an inversion circuit between the host and this LSI. Rev. 1.00 Dec. 13, 2007 Page 117 of 380 REJ09B0430-0100 Section 6 ROM 3. When the boot program is initiated, the chip measures the low-level period of asynchronous SCI communication data (H'00) transmitted continuously from the host. The chip then calculates the bit rate of transmission from the host, and adjusts the SCI3 bit rate to match that of the host. The reset should end with the RXD pin high. The RXD and TXD pins should be pulled up on the board if necessary. After the reset is complete, it takes approximately 100 states before the chip is ready to measure the low-level period. 4. After matching the bit rates, the chip transmits one H'00 byte to the host to indicate the completion of bit rate adjustment. The host should confirm that this adjustment end indication (H'00) has been received normally, and transmit one H'55 byte to the chip. If reception could not be performed normally, initiate boot mode again by a reset. Depending on the host's transfer bit rate and system clock frequency of this LSI, there will be a discrepancy between the bit rates of the host and the chip. To operate the SCI properly, set the host's transfer bit rate and system clock frequency of this LSI within the ranges listed in table 6.3. 5. In boot mode, a part of the on-chip RAM area is used by the boot program. The area H'F780 to H'FEEF is the area to which the programming control program is transferred from the host. The boot program area cannot be used until the execution state in boot mode switches to the programming control program. 6. Before branching to the programming control program, the chip terminates transfer operations by SCI3 (by clearing the RE and TE bits in SCR to 0), however the adjusted bit rate value remains set in BRR. Therefore, the programming control program can still use it for transfer of write data or verify data with the host. The TXD pin is high (PCR42 = 1, P42 = 1). The contents of the CPU general registers are undefined immediately after branching to the programming control program. These registers must be initialized at the beginning of the programming control program, as the stack pointer (SP), in particular, is used implicitly in subroutine calls, etc. 7. Boot mode can be cleared by a reset. End the reset after driving the reset pin low, waiting at least 20 states, and then setting the TEST pin and P95 pin. Boot mode is also cleared when a WDT overflow occurs. 8. Do not change the TEST pin and P95 pin input levels in boot mode. Rev. 1.00 Dec. 13, 2007 Page 118 of 380 REJ09B0430-0100 Section 6 ROM Table 6.2 Item Boot Mode Operation Host Operation Processing Contents Communication Contents LSI Operation Processing Contents Branches to boot program at reset-start. Boot mode initiation Boot program initiation Bit rate adjustment Continuously transmits data H'00 at specified bit rate. H'00, H'00 . . . H'00 Transmits data H'55 when data H'00 is received error-free. H'00 H'55 * Measures low-level period of receive data H'00. * Calculates bit rate and sets BRR in SCI3. * Transmits data H'00 to host as adjustment end indication. Flash memory erase Boot program erase error H'FF H'AA reception H'AA Checks flash memory data, erases all flash memory blocks in case of written data existing, and transmits data H'AA to host. (If erase could not be done, transmits data H'FF to host and aborts operation.) Transfer of number of bytes of programming control program Transmits number of bytes (N) of programming control program to be transferred as 2-byte data (low-order byte following high-order byte) Upper bytes, lower bytes Echoback Echobacks the 2-byte data received to host. Transmits 1-byte of programming control program (repeated for N times) H'XX Echoback Echobacks received data to host and also transfers it to RAM. (repeated for N times) H'AA reception H'AA Transmits data H'AA to host. Branches to programming control program transferred to on-chip RAM and starts execution. Rev. 1.00 Dec. 13, 2007 Page 119 of 380 REJ09B0430-0100 Section 6 ROM Table 6.3 Oscillation Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible (fOSC) Oscillation Frequency Range of LSI (fOSC) 8 to 10 MHz 4 to 10 MHz 2 to 10 MHz Host Bit Rate 4,800 bps 2,400 bps 1,200 bps 6.4.2 Programming/Erasing in User Program Mode User program mode means the execution state of the user program. On-board programming/erasing of an individual flash memory block can also be performed in user program mode by branching to a user program/erase control program. The user must set branching conditions and provide on-board means of supplying programming data. The flash memory must contain the user program/erase control program or a program that provides the user program/erase control program from external memory. As the flash memory itself cannot be read during programming/erasing, transfer the user program/erase control program to on-chip RAM, as in boot mode. Figure 6.4 shows a sample procedure for programming/erasing in user program mode. Prepare a user program/erase control program in accordance with the description in section 6.5, Flash Memory Programming/Erasing. Rev. 1.00 Dec. 13, 2007 Page 120 of 380 REJ09B0430-0100 Section 6 ROM Reset-start No Program/erase? Yes Transfer user program/erase control program to RAM Branch to flash memory application program Branch to user program/erase control program in RAM Execute user program/erase control program (flash memory rewrite) Branch to flash memory application program Figure 6.4 Programming/Erasing Flowchart Example in User Program Mode 6.5 Flash Memory Programming/Erasing A software method using the CPU is employed to program and erase flash memory in the onboard programming modes. Depending on the FLMCR1 setting, the flash memory operates in one of the following four modes: Program mode, program-verify mode, erase mode, and erase-verify mode. The programming control program in boot mode and the user program/erase control program in user program mode use these operating modes in combination to perform programming/erasing. Flash memory programming and erasing should be performed in accordance with the descriptions in section 6.5.1, Program/Program-Verify and section 6.5.2, Erase/Erase-Verify, respectively. Rev. 1.00 Dec. 13, 2007 Page 121 of 380 REJ09B0430-0100 Section 6 ROM 6.5.1 Program/Program-Verify When writing data or programs to the flash memory, the program/program-verify flowchart shown in figure 6.5 should be followed. Performing programming operations according to this flowchart will enable data or programs to be written to the flash memory without subjecting the chip to voltage stress or sacrificing program data reliability. 1. Programming must be done to an empty address. Do not reprogram an address to which programming has already been performed. 2. Programming should be carried out 128 bytes at a time. A 128-byte data transfer must be performed even if writing fewer than 128 bytes. In this case, H'FF data must be written to the extra addresses. 3. Prepare the following data storage areas in RAM: A 128-byte programming data area, a 128byte reprogramming data area, and a 128-byte additional-programming data area. Perform reprogramming data computation according to table 6.4, and additional programming data computation according to table 6.5. 4. Consecutively transfer 128 bytes of data in byte units from the reprogramming data area or additional-programming data area to the flash memory. The program address and 128-byte data are latched in the flash memory. The lower 8 bits of the start address in the flash memory destination area must be H'00 or H'80. 5. The time during which the P bit is set to 1 is the programming time. Table 6.6 shows the allowable programming times. 6. The watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc. An overflow cycle of approximately 6.6 ms is allowed. 7. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower one bit is B'0. Verify data can be read in word or longword units from the address to which a dummy write was performed. 8. The maximum number of repetitions of the program/program-verify sequence of the same bit is 1,000. Rev. 1.00 Dec. 13, 2007 Page 122 of 380 REJ09B0430-0100 Section 6 ROM Write pulse application subroutine Apply Write Pulse WDT enable Set PSU bit in FLMCR1 Wait 50 s Set P bit in FLMCR1 Wait (Wait time=programming time) Clear P bit in FLMCR1 Wait 5 s Clear PSU bit in FLMCR1 Wait 5 s Disable WDT START Set SWE bit in FLMCR1 Wait 1 s Store 128-byte program data in program data area and reprogram data area n1 m0 Write 128-byte data in RAM reprogram data area consecutively to flash memory Apply Write pulse Set PV bit in FLMCR1 Wait 4 s Set block start address as verify address nn+1 H'FF dummy write to verify address End Sub Wait 2 s Read verify data Increment address Verify data = write data? No m1 No Yes n6? Yes Additional-programming data computation Reprogram data computation No 128-byte data verification completed? Yes Clear PV bit in FLMCR1 Wait 2 s n 6? Yes Successively write 128-byte data from additionalprogramming data area in RAM to flash memory Sub-Routine-Call Apply Write Pulse No Yes No m= 0 ? Yes Clear SWE bit in FLMCR1 Wait 100 s End of programming n 1000 ? No Clear SWE bit in FLMCR1 Wait 100 s Programming failure Figure 6.5 Program/Program-Verify Flowchart Rev. 1.00 Dec. 13, 2007 Page 123 of 380 REJ09B0430-0100 Section 6 ROM Table 6.4 Reprogram Data Computation Table Verify Data 0 1 0 1 Reprogram Data 1 0 1 1 Comments Programming completed Reprogram bit -- Remains in erased state Program Data 0 0 1 1 Table 6.5 Additional-Program Data Computation Table Verify Data 0 1 0 1 Additional-Program Data 0 1 1 1 Comments Additional-program bit No additional programming No additional programming No additional programming Reprogram Data 0 0 1 1 Table 6.6 Programming Time In Additional Programming 10 -- Comments n Programming (Number of Writes) Time 1 to 6 7 to 1,000 30 200 Note: Time shown in s. Rev. 1.00 Dec. 13, 2007 Page 124 of 380 REJ09B0430-0100 Section 6 ROM 6.5.2 Erase/Erase-Verify When erasing flash memory, the erase/erase-verify flowchart shown in figure 6.6 should be followed. 1. Prewriting (setting erase block data to all 0s) is not necessary. 2. Erasing is performed in block units. Make only a single-bit specification in the erase block register (EBR). To erase multiple blocks, each block must be erased in turn. 3. The time during which the E bit is set to 1 is the flash memory erase time. 4. The watchdog timer (WDT) is set to prevent overerasing due to program runaway, etc. An overflow cycle of approximately 19.8 ms is allowed. 5. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower 1 bit is B'0. Verify data can be read in word or longword units from the address to which a dummy write was performed. 6. If the read data is not erased successfully, set erase mode again, and repeat the erase/eraseverify sequence as before. The maximum number of repetitions of the erase/erase-verify sequence is 100. 6.5.3 Interrupt Handling when Programming/Erasing Flash Memory All interrupts are disabled while flash memory is being programmed or erased, or while the boot program is executing, for the following three reasons: 1. Interrupt during programming/erasing may cause a violation of the programming or erasing algorithm, with the result that normal operation cannot be assured. 2. If interrupt exception handling starts before the vector address is written or during programming/erasing, a correct vector cannot be fetched and the CPU malfunctions. 3. If an interrupt occurs during boot program execution, normal boot mode sequence cannot be carried out. Rev. 1.00 Dec. 13, 2007 Page 125 of 380 REJ09B0430-0100 Section 6 ROM Erase start SWE bit 1 Wait 1 s n1 Set EBR Enable WDT ESU bit 1 Wait 100 s E bit 1 Wait 10 ms E bit 0 Wait 10 s ESU bit 0 Wait 10 s Disable WDT EV bit 1 Wait 20 s Set block start address as verify address H'FF dummy write to verify address Wait 2 s Read verify data No Increment address Verify data = all 1s ? Yes nn+1 No Last address of block ? Yes EV bit 0 Wait 4 s EV bit 0 Wait 4s No All erase block erased ? Yes n 100 ? No Yes SWE bit 0 Wait 100 s End of erasing SWE bit 0 Wait 100 s Erase failure Figure 6.6 Erase/Erase-Verify Flowchart Rev. 1.00 Dec. 13, 2007 Page 126 of 380 REJ09B0430-0100 Section 6 ROM 6.6 Program/Erase Protection There are three kinds of flash memory program/erase protection; hardware protection, software protection, and error protection. 6.6.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted because of a transition to reset, subactive mode, subsleep mode, watch mode, or standby mode. Flash memory control register 1 (FLMCR1), flash memory control register 2 (FLMCR2), and erase block register (EBR) are initialized. In a reset via the RES pin, the reset state is not entered unless the RES pin is held low until oscillation stabilizes after powering on. In the case of a reset during operation, hold the RES pin low for the RES pulse width specified in the AC Characteristics section. 6.6.2 Software Protection Software protection can be implemented against programming/erasing of all flash memory blocks by clearing the SWE bit in FLMCR1. When software protection is in effect, setting the P or E bit in FLMCR1 does not cause a transition to program mode or erase mode. By setting the erase block register (EBR), erase protection can be set for individual blocks. When EBR is set to H'00, erase protection is set for all blocks. 6.6.3 Error Protection In error protection, an error is detected when CPU runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. Aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. When the following errors are detected during programming/erasing of flash memory, the FLER bit in FLMCR2 is set to 1, and the error protection state is entered. * When the flash memory of the relevant address area is read during programming/erasing (including vector read and instruction fetch) * Immediately after exception handling excluding a reset during programming/erasing * When a SLEEP instruction is executed during programming/erasing Rev. 1.00 Dec. 13, 2007 Page 127 of 380 REJ09B0430-0100 Section 6 ROM The FLMCR1, FLMCR2, and EBR settings are retained, however program mode or erase mode is aborted at the point at which the error occurred. Program mode or erase mode cannot be re-entered by re-setting the P or E bit. However, PV and EV bit setting is enabled, and a transition can be made to verify mode. Error protection can be cleared only by a power-on reset. 6.7 Programmer Mode In programmer mode, a PROM programmer can be used to perform programming/erasing via a socket adapter, just as a discrete flash memory. Use a PROM programmer that supports the MCU device type with the on-chip Renesas Technology (former Hitachi Ltd.) 64-kbyte flash memory (FZTAT64V3). A 10-MHz input clock is required. For the conditions for transition to programmer mode, see table 6.1. 6.7.1 Socket Adapter The socket adapter converts the pin allocation of the HD64F38704 and HD64F38702 to that of the discrete flash memory HN28F101. The address of the on-chip flash memory is H'0000 to H'7FFF. Figure 6.7 shows a socket-adapter-pin correspondence diagram. 6.7.2 Programmer Mode Commands The following commands are supported in programmer mode. * * * * Memory Read Mode Auto-Program Mode Auto-Erase Mode Status Read Mode Status polling is used for auto-programming, auto-erasing, and status read modes. In status read mode, detailed internal information is output after the execution of auto-programming or autoerasing. Table 6.7 shows the sequence of each command. In auto-programming mode, 129 cycles are required since 128 bytes are written at the same time. In memory read mode, the number of cycles depends on the number of address write cycles (n). Rev. 1.00 Dec. 13, 2007 Page 128 of 380 REJ09B0430-0100 Section 6 ROM Table 6.7 Command Name Memory read Autoprogram Auto-erase Command Sequence in Programmer Mode Number of Cycles Mode 1+n 129 2 Write Write Write Write 1st Cycle Address X X X X Data H'00 H'40 H'20 H'71 Mode Read Write Write Write 2nd Cycle Address RA WA X X Data Dout Din H'20 H'71 Status read 2 [Legend] n: Number of address write cycles Rev. 1.00 Dec. 13, 2007 Page 129 of 380 REJ09B0430-0100 Section 6 ROM H8/38704F, H8/38702F Pin No. FP-64A FP-64E 31 25 49 40 39 38 37 36 35 34 33 57 58 10 11 12 13 14 15 32 59 30 29 28 27 26 60 16 61 2 7 17 50 54 4 55 62 63 64 6, 5 8 Other than above Pin Name Socket Adapter (Conversion to 32-Pin Arrangement) HN28F101 (32 Pins) Pin Name FWE Pin No. 1 26 2 3 31 13 14 15 17 18 19 20 21 12 11 10 9 8 7 6 5 27 24 23 25 4 28 29 22 32 16 P71 P77 P90 P60 P61 P62 P63 P64 P65 P66 P67 P40 P41 P32 P33 P34 P35 P36 P37 P70 P42 P72 P73 P74 P75 P76 P43 Vcc AVcc X1 TEST V1 P91 P95 Vss Vss PB0 PB1 PB2 OSC1,OSC2 RES (OPEN) Oscillator circuit Power-on reset circuit A9 A16 A15 WE I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 A0 A1 A2 A3 A4 A5 A6 A7 A8 OE A10 A11 A12 A13 A14 CE Vcc Vss Legend: FWE: I/O7 to I/O0: A16 to A0: CE: OE: WE: Flash-write enable Data input/output Address input Chip enable Output enable Write enable Note: The oscillation frequency of the oscillator circuit should be 10 MHz. Figure 6.7 Socket Adapter Pin Correspondence Diagram (H8/38704F, H8/38702F) Rev. 1.00 Dec. 13, 2007 Page 130 of 380 REJ09B0430-0100 Section 6 ROM 6.7.3 Memory Read Mode After completion of auto-program/auto-erase/status read operations, a transition is made to the command wait state. When reading memory contents, a transition to memory read mode must first be made with a command write, after which the memory contents are read. Once memory read mode has been entered, consecutive reads can be performed. 1. In memory read mode, command writes can be performed in the same way as in the command wait state. 2. After powering on, memory read mode is entered. 3. Tables 6.8 to 6.10 show the AC characteristics. Table 6.8 AC Characteristics in Transition to Memory Read Mode (Conditions: VCC = 3.3 V 0.3 V, VSS = 0 V, Ta = 25C 5C) Item Command write cycle CE hold time CE setup time Data hold time Data setup time Write pulse width WE rise time WE fall time Symbol tnxtc tceh tces tdh tds twep tr tf Min 20 0 0 50 50 70 -- -- Max -- -- -- -- -- -- 30 30 Unit s ns ns ns ns ns ns ns Test Condition Figure 6.8 Rev. 1.00 Dec. 13, 2007 Page 131 of 380 REJ09B0430-0100 Section 6 ROM Command write A15 to A0 tces CE OE tf WE tds I/O7 to I/O0 tdh twep tr tceh tnxtc Memory read mode Address stable Note: Data is latched on the rising edge of WE. Figure 6.8 Timing Waveforms for Memory Read after Command Write Table 6.9 AC Characteristics in Transition from Memory Read Mode to Another Mode (Conditions: VCC = 3.3 V 0.3 V, VSS = 0 V, Ta = 25C 5C) Item Command write cycle CE hold time CE setup time Data hold time Data setup time Write pulse width WE rise time WE fall time Symbol tnxtc tceh tces tdh tds twep tr tf Min 20 0 0 50 50 70 -- -- Max -- -- -- -- -- -- 30 30 Unit s ns ns ns ns ns ns ns Test Condition Figure 6.9 Rev. 1.00 Dec. 13, 2007 Page 132 of 380 REJ09B0430-0100 Section 6 ROM Memory read mode A15 to A0 Address stable tnxtc CE OE Other mode command write tces tceh tf WE twep tr tds I/O7 to I/O0 tdh Note: Do not enable WE and OE at the same time. Figure 6.9 Timing Waveforms in Transition from Memory Read Mode to Another Mode Table 6.10 AC Characteristics in Memory Read Mode (Conditions: VCC = 3.3 V 0.3 V, VSS = 0 V, Ta = 25C 5C) Item Access time CE output delay time OE output delay time Output disable delay time Data output hold time Symbol tacc tce toe tdf toh Min -- -- -- -- 5 Max 20 150 150 100 -- Unit s ns ns ns ns Test Condition Figures 6.10 and 6.11 A15 to A0 Address stable Address stable CE OE WE I/O7 to I/O0 tacc toh tacc toh Figure 6.10 Timing Waveforms in CE and OE Enable State Read Rev. 1.00 Dec. 13, 2007 Page 133 of 380 REJ09B0430-0100 Section 6 ROM A15 to A0 Address stable tce Address stable tce CE toe OE WE I/O7 to I/O0 tacc tacc toh tdf toh tdf toe Figure 6.11 Timing Waveforms in CE and OE Clock System Read 6.7.4 Auto-Program Mode 1. When reprogramming previously programmed addresses, perform auto-erasing before autoprogramming. 2. Perform auto-programming once only on the same address block. It is not possible to program an address block that has already been programmed. 3. In auto-program mode, 128 bytes are programmed simultaneously. This should be carried out by executing 128 consecutive byte transfers. A 128-byte data transfer is necessary even when programming fewer than 128 bytes. In this case, H'FF data must be written to the extra addresses. 4. The lower 7 bits of the transfer address must be low. If a value other than an effective address is input, processing will switch to a memory write operation but a write error will be flagged. 5. Memory address transfer is performed in the second cycle (figure 6.12). Do not perform transfer after the third cycle. 6. Do not perform a command write during a programming operation. 7. Perform one auto-program operation for a 128-byte block for each address. Two or more additional programming operations cannot be performed on a previously programmed address block. 8. Confirm normal end of auto-programming by checking I/O6. Alternatively, status read mode can also be used for this purpose (I/O7 status polling uses the auto-program operation end decision pin). 9. Status polling I/O6 and I/O7 pin information is retained until the next command write. As long as the next command write has not been performed, reading is possible by enabling CE and OE. 10. Table 6.11 shows the AC characteristics. Rev. 1.00 Dec. 13, 2007 Page 134 of 380 REJ09B0430-0100 Section 6 ROM Table 6.11 AC Characteristics in Auto-Program Mode (Conditions: VCC = 3.3 V 0.3 V, VSS = 0 V, Ta = 25C 5C) Item Command write cycle CE hold time CE setup time Data hold time Data setup time Write pulse width Status polling start time Symbol tnxtc tceh tces tdh tds twep twsts tas tah twrite tr tf Min 20 0 0 50 50 70 1 -- 0 60 1 -- -- Max -- -- -- -- -- -- -- 150 -- -- 3000 30 30 Unit s ns ns ns ns ns ms ns ns ns ms ns ns Test Condition Figure 6.12 Status polling access time tspa Address setup time Address hold time Memory write time WE rise time WE fall time A15 to A0 tces CE OE tf WE tds I/O7 tdh tceh tnxtc Address stable tnxtc twep tr tas tah Data transfer 1 to 128 bytes twsts tspa twrite Write operation end decision signal I/O6 Write normal end decision signal I/O5 to I/O0 H'40 H'00 Figure 6.12 Timing Waveforms in Auto-Program Mode Rev. 1.00 Dec. 13, 2007 Page 135 of 380 REJ09B0430-0100 Section 6 ROM 6.7.5 Auto-Erase Mode 1. Auto-erase mode supports only entire memory erasing. 2. Do not perform a command write during auto-erasing. 3. Confirm normal end of auto-erasing by checking I/O6. Alternatively, status read mode can also be used for this purpose (I/O7 status polling uses the auto-erase operation end decision pin). 4. Status polling I/O6 and I/O7 pin information is retained until the next command write. As long as the next command write has not been performed, reading is possible by enabling CE and OE. 5. Table 6.12 shows the AC characteristics. Table 6.12 AC Characteristics in Auto-Erase Mode (Conditions: VCC = 3.3 V 0.3 V, VSS = 0 V, Ta = 25C 5C) Item Command write cycle CE hold time CE setup time Data hold time Data setup time Write pulse width Status polling start time Symbol tnxtc tceh tces tdh tds twep tests terase tr tf Min 20 0 0 50 50 70 1 -- 100 -- -- Max -- -- -- -- -- -- -- 150 40000 30 30 Unit s ns ns ns ns ns ms ns ms ns ns Test Condition Figure 6.13 Status polling access time tspa Memory erase time WE rise time WE fall time Rev. 1.00 Dec. 13, 2007 Page 136 of 380 REJ09B0430-0100 Section 6 ROM A15 to A0 tces CE OE tf WE tds I/O7 Erase end decision signal I/O6 Erase normal end decision signal I/O5 to I/O0 H'20 H'20 H'00 tdh terase twep tr tests tspa tceh tnxtc tnxtc Figure 6.13 Timing Waveforms in Auto-Erase Mode 6.7.6 Status Read Mode 1. Status read mode is provided to identify the kind of abnormal end. Use this mode when an abnormal end occurs in auto-program mode or auto-erase mode. 2. The return code is retained until a command write other than command write in status read mode is executed. 3. Table 6.13 shows the AC characteristics and table 6.14 shows the return codes. Rev. 1.00 Dec. 13, 2007 Page 137 of 380 REJ09B0430-0100 Section 6 ROM Table 6.13 AC Characteristics in Status Read Mode (Conditions: VCC = 3.3 V 0.3 V, VSS = 0 V, Ta = 25C 5C) Item Symbol Min 20 0 0 50 50 70 -- -- -- -- -- Max -- -- -- -- -- -- 150 100 150 30 30 Unit s ns ns ns ns ns ns ns ns ns ns Test Condition Figure 6.14 Read time after command tnxtc write CE hold time CE setup time Data hold time Data setup time Write pulse width OE output delay time Disable delay time CE output delay time WE rise time WE fall time tceh tces tdh tds twep toe tdf tce tr tf A15 to A0 tces CE tce OE tf WE tds I/O7 to I/O0 H'71 tdh tds H'71 tdh twep tr tf twep tr toe tceh tnxtc tces tceh tnxtc tnxtc tdf Note: I/O2 and I/O3 are undefined. Figure 6.14 Timing Waveforms in Status Read Mode Rev. 1.00 Dec. 13, 2007 Page 138 of 380 REJ09B0430-0100 Section 6 ROM Table 6.14 Return Codes in Status Read Mode Pin Name I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 Initial Value 0 0 0 0 0 0 0 0 Description 1: Abnormal end 0: Normal end 1: Command error 0: Otherwise 1: Programming error 0: Otherwise 1: Erasing error 0: Otherwise Undefined Undefined 1: Over counting of writing or erasing 0: Otherwise 1: Effective address error 0: Otherwise 6.7.7 Status Polling 1. The I/O7 status polling flag indicates the operating status in auto-program/auto-erase mode. 2. The I/O6 status polling flag indicates a normal or abnormal end in auto-program/auto-erase mode. Table 6.15 Status Polling Output I/O7 0 1 1 0 I/O6 0 0 1 1 I/O0 to I/O5 0 0 0 0 Status During internal operation Abnormal end Normal end -- Rev. 1.00 Dec. 13, 2007 Page 139 of 380 REJ09B0430-0100 Section 6 ROM 6.7.8 Programmer Mode Transition Time Commands cannot be accepted during the oscillation stabilization period or the programmer mode setup period. After the programmer mode setup time, a transition is made to memory read mode. Table 6.16 Stipulated Transition Times to Command Wait State Item Symbol Min 10 5 tbmv tdwn 10 0 Max -- -- -- -- Unit ms ms ms ms Test Condition Figure 6.15 Oscillation stabilization time tosc1 (crystal resonator) Oscillation stabilization time (ceramic resonator) Programmer mode setup time VCC hold time tosc1 VCC RES tbmv Auto-program mode Auto-erase mode tdwn Figure 6.15 Oscillation Stabilization Time, Boot Program Transfer Time, and Power-Down Sequence 6.7.9 Notes on Memory Programming 1. When performing programming using programmer mode on a chip that has been programmed/erased in on-board programming mode, auto-erasing is recommended before carrying out auto-programming. 2. The flash memory is initially in the erased state when the device is shipped by Renesas. For other chips for which the erasure history is unknown, it is recommended that auto-erasing be executed to check and supplement the initialization (erase) level. Rev. 1.00 Dec. 13, 2007 Page 140 of 380 REJ09B0430-0100 Section 6 ROM 6.8 Power-Down States for Flash Memory In user mode, the flash memory will operate in either of the following states: * Normal operating mode The flash memory can be read and written to at high speed. * Power-down operating mode The power supply circuit of flash memory can be partly halted. As a result, flash memory can be read with low power consumption. * Standby mode All flash memory circuits are halted. Table 6.17 shows the correspondence between the operating modes of this LSI and the flash memory. In subactive mode, the flash memory can be set to operate in power-down mode with the PDWND bit in FLPWCR. When the flash memory returns to its normal operating state from power-down mode or standby mode, a period to stabilize operation of the power supply circuits that were stopped is needed. When the flash memory returns to its normal operating state, bits STS2 to STS0 in SYSCR1 must be set to provide a wait time of at least 20 s, even when the external clock is being used. Table 6.17 Flash Memory Operating States Flash Memory Operating State LSI Operating State Active mode Subactive mode Sleep mode Subsleep mode Standby mode Watch mode PDWND = 0 (Initial value) Normal operating mode Power-down mode Normal operating mode Standby mode Standby mode Standby mode PDWND = 1 Normal operating mode Normal operating mode Normal operating mode Standby mode Standby mode Standby mode Rev. 1.00 Dec. 13, 2007 Page 141 of 380 REJ09B0430-0100 Section 6 ROM Rev. 1.00 Dec. 13, 2007 Page 142 of 380 REJ09B0430-0100 Section 7 RAM Section 7 RAM This LSI has an on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit data bus, enabling two-state access by the CPU to both byte data and word data. Product Classification Flash memory version H8/38704F H8/38702F Mask ROM version H8/38704 H8/38703 H8/38702 H8/38702S H8/38701S H8/38700S RAM Size 1 kbyte 1 kbyte 1 kbyte 1 kbyte 1 kbyte 512 bytes 512 bytes 512 bytes RAM Address H'FB80 to H'FF7F H'FB80 to H'FF7F H'FB80 to H'FF7F H'FB80 to H'FF7F H'FB80 to H'FF7F H'FD80 to H'FF7F H'FD80 to H'FF7F H'FD80 to H'FF7F Rev. 1.00 Dec. 13, 2007 Page 143 of 380 REJ09B0430-0100 Section 7 RAM 7.1 Block Diagram Figure 7.1 shows a block diagram of the on-chip RAM. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) H'FB80 H'FB82 H'FB80 H'FB82 H'FB81 H'FB83 On-chip RAM H'FF7E H'FF7E Even address H'FF7F Odd address Figure 7.1 Block Diagram of RAM Rev. 1.00 Dec. 13, 2007 Page 144 of 380 REJ09B0430-0100 Section 8 I/O Ports Section 8 I/O Ports This LSI is provided with three 8-bit I/O ports, one 7-bit I/O port, one 4-bit I/O port, one 3-bit I/O port, one 1-bit I/O port, one 4-bit input-only port, one 1-bit input-only port, and one 6-bit outputonly port. Each port is configured by the port control register (PCR) that controls input and output, and the port data register (PDR) that stores output data. Input or output can be assigned to individual bits. See section 2.8.3, Bit-Manipulation Instructions, for information on executing bit-manipulation instructions to write data in PCR or PDR. Block diagrams of each port are given in appendix B, I/O Port Block Diagrams. Table 8.1 lists the functions of each port. Rev. 1.00 Dec. 13, 2007 Page 145 of 380 REJ09B0430-0100 Section 8 I/O Ports Table 8.1 Port Functions Function Switching Registers Port Port 3 Description * * 7-bit I/O port Input pull-up MOS option Pins P37/AEVL P36/AEVH P35 P34 P33 P32/TMOFH P31/TMOFL Other Functions Asynchronous event PMR3 counter event inputs AEVL, AEVH Timer F output compare output External interrupt 0 SCI3 data output (TXD32), data input (RXD32), clock input/output (SCK32) Wakeup input (WKP7 to WKP0) None None None None PMR3 PMR2 SCR3 SMR PMR5 Port 4 * * 1-bit input-only port 3-bit I/O port P43/IRQ0 P42/TXD32 P41/RXD32 P40/SCK32 P57 to P50/ WKP7 to WKP0 P67 to P60 P77 to P70 P80 P95 to P92 Port 5 * * 8-bit I/O port Input pull-up MOS option 8-bit I/O port Input pull-up MOS option 8-bit I/O port 1-bit I/O port 6-bit output-only port Port 6 Port 7 Port 8 Port 9 * * * * * PMR9 AMR PMRB AMR AMR P91, P90/ 10-bit PWM output PWM2, PWM1 Port A Port B * * 4-bit I/O port 4-bit input-only port PA3 to PA0 PB3/AN3/ IRQ1 PB2/AN2 PB1/AN1 PB0/AN0 None A/D converter analog input External interrupt 1 A/D converter analog input A/D converter analog input Rev. 1.00 Dec. 13, 2007 Page 146 of 380 REJ09B0430-0100 Section 8 I/O Ports 8.1 Port 3 Port 3 is an I/O port also functioning as an asynchronous event counter input pin and timer F output pin. Figure 8.1 shows its pin configuration. P37/AEVL P36/AEVH P35 Port 3 P34 P33 P32/TMOFH P31/TMOFL Figure 8.1 Port 3 Pin Configuration Port 3 has the following registers. * * * * * Port data register 3 (PDR3) Port control register 3 (PCR3) Port pull-up control register 3 (PUCR3) Port mode register 3 (PMR3) Port mode register 2 (PMR2) Rev. 1.00 Dec. 13, 2007 Page 147 of 380 REJ09B0430-0100 Section 8 I/O Ports 8.1.1 Port Data Register 3 (PDR3) PDR3 is a register that stores data of port 3. Bit 7 6 5 4 3 2 1 0 Bit Name P37 P36 P35 P34 P33 P32 P31 Initial Value 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Reserved Description If port 3 is read while PCR3 bits are set to 1, the values stored in PDR3 are read, regardless of the actual pin states. If port 3 is read while PCR3 bits are cleared to 0, the pin states are read. 8.1.2 Port Control Register 3 (PCR3) PCR3 controls whether each of the port 3 pins functions as an input pin or output pin. Bit 7 6 5 4 3 2 1 0 Bit Name PCR37 PCR36 PCR35 PCR34 PCR33 PCR32 PCR31 Initial Value 0 0 0 0 0 0 0 R/W W W W W W W W W Reserved The write value should always be 0. Description Setting a PCR3 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. The settings in PCR3 and in PDR3 are valid only when the corresponding pin is designated in PMR3 as a general I/O pin. PCR3 is a write-only register. Bits 7 to 1 are always read as 1. Rev. 1.00 Dec. 13, 2007 Page 148 of 380 REJ09B0430-0100 Section 8 I/O Ports 8.1.3 Port Pull-Up Control Register 3 (PUCR3) PUCR3 controls whether the pull-up MOS of each of the port 3 pins is on or off. Bit 7 6 5 4 3 2 1 0 Bit Name PUCR37 PUCR36 PUCR35 PUCR34 PUCR33 PUCR32 PUCR31 Initial Value 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W W Reserved The write value should always be 0. Description When a PCR3 bit is cleared to 0, setting the corresponding PUCR3 bit to 1 turns on the pull-up MOS for the corresponding pin, while clearing the bit to 0 turns off the pull-up MOS. Rev. 1.00 Dec. 13, 2007 Page 149 of 380 REJ09B0430-0100 Section 8 I/O Ports 8.1.4 Port Mode Register 3 (PMR3) PMR3 controls the selection of pin functions for port 3 pins. Bit 7 Bit Name AEVL Initial Value 0 R/W R/W Description P37/AEVL Pin Function Switch This bit selects whether pin P37/AEVL is used as P37 or as AEVL. 0: P37 I/O pin 1: AEVL input pin 6 AEVH 0 R/W P36/AEVH Pin Function Switch This bit selects whether pin P36/AEVH is used as P36 or as AEVH. 0: P36 I/O pin 1: AEVH input pin 5 to 3 2 TMOFH 0 W R/W Reserved The write value should always be 0. P32/TMOFH Pin Function Switch This bit selects whether pin P32/TMOFH is used as P32 or as TMOFH. 0: P32 I/O pin 1: TMOFH output pin 1 TMOFL 0 R/W P31/TMOFL Pin Function Switch This bit selects whether pin P31/TMOFL is used as P31 or as TMOFL. 0: P31 I/O pin 1: TMOFL output pin 0 W Reserved The write value should always be 0. Rev. 1.00 Dec. 13, 2007 Page 150 of 380 REJ09B0430-0100 Section 8 I/O Ports 8.1.5 Port Mode Register 2 (PMR2) PMR2 controls the PMOS on/off state for the P35 pin, selects a pin function for the P43/IRQ0 pin, and selects a clock of the watchdog timer. Bit 7, 6 Bit Name Initial Value All 1 R/W Description Reserved These bits are always read as 1 and cannot be modified. 5 POF1 0 R/W P35 Pin PMOS Control This bit controls the on/off state of the PMOS of the P35 pin output buffer. 0: CMOS output 1: NMOS open-drain output 4, 3 All 1 Reserved These bits are always read as 1 and cannot be modified. 2 WDCKS 0 R/W Watchdog Timer Source Clock Select This bit selects the input clock for the watchdog timer. 0: /8,192 1: w/32 1 0 IRQ0 0 W R/W Reserved The write value should always be 0. P43/IRQ0 Pin Function Switch This bit selects whether pin P43/IRQ0 is used as P43 or as IRQ0. 0: P43 input pin 1: IRQ0 input pin Rev. 1.00 Dec. 13, 2007 Page 151 of 380 REJ09B0430-0100 Section 8 I/O Ports 8.1.6 Pin Functions The port 3 pin functions are shown below. * P37/AEVL pin The pin function depends on the combination of bit AEVL in PMR3 and bit PCR37 in PCR3. AEVL PCR37 Pin Function [Legend] x: Don't care. 0 P37 input pin 0 1 P37 output pin 1 x AEVL input pin * P36/AEVH pin The pin function depends on the combination of bit AEVH in PMR3 and bit PCR36 in PCR3. AEVH PCR36 Pin Function [Legend] x: Don't care. 0 P36 input pin 0 1 P36 output pin 1 x AEVH input pin * P35 to P33 pins The pin function depends on the corresponding bit in PCR3. (n = 5 to 3) PCR3n Pin Function 0 P3n input pin 1 P3n output pin * P32/TMOFH pin The pin function depends on the combination of bit TMOFH in PMR3 and bit PCR32 in PCR3. TMOFH PCR32 Pin Function [Legend] x: Don't care. 0 P32 input pin 0 1 P32 output pin 1 x TMOFH output pin Rev. 1.00 Dec. 13, 2007 Page 152 of 380 REJ09B0430-0100 Section 8 I/O Ports * P31/TMOFL pin The pin function depends on the combination of bit TMOFL in PMR3 and bit PCR31 in PCR3. TMOFL PCR31 Pin Function [Legend] x: Don't care. 0 P31 input pin 0 1 P31 output pin 1 x TMOFL output pin 8.1.7 Input Pull-Up MOS Port 3 has an on-chip input pull-up MOS function that can be controlled by software. When the PCR3 bit is cleared to 0, setting the corresponding PUCR3 bit to 1 turns on the input pull-up MOS for that pin. The input pull-up MOS function is in the off state after a reset. (n = 7 to 1) PCR3n PUCR3n Input Pull-Up MOS [Legend] x: Don't care. 0 Off 0 1 On 1 x Off Rev. 1.00 Dec. 13, 2007 Page 153 of 380 REJ09B0430-0100 Section 8 I/O Ports 8.2 Port 4 Port 4 is an I/O port also functioning as an interrupt input pin and SCI I/O pin. Figure 8.2 shows its pin configuration. P43/IRQ0 P42/TXD32 Port 4 P41/RXD32 P40/SCK32 Figure 8.2 Port 4 Pin Configuration Port 4 has the following registers. * Port data register 4 (PDR4) * Port control register 4 (PCR4) * Serial port control register (SPCR) 8.2.1 Port Data Register 4 (PDR4) PDR4 is a register that stores data of port 4. Bit 7 to 4 3 2 1 0 Bit Name P43 P42 P41 P40 Initial Value 1 1 0 0 0 R/W R R/W R/W R/W Description Reserved These bits are always read as 1. If port 4 is read while PCR4 bits are set to 1, the values stored in PDR4 are read, regardless of the actual pin states. If port 4 is read while PCR4 bits are cleared to 0, the pin states are read. Rev. 1.00 Dec. 13, 2007 Page 154 of 380 REJ09B0430-0100 Section 8 I/O Ports 8.2.2 Port Control Register 4 (PCR4) PCR4 controls whether each of the port 4 pins functions as an input pin or output pin. Bit 7 to 3 2 1 0 Bit Name PCR42 PCR41 PCR40 Initial Value All 1 0 0 0 R/W W W W Description Reserved These bits are always read as 1. Setting a PCR4 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. The settings in PCR4 and in PDR4 are valid only when the corresponding pin is designated in SCR3 and SCR2 as a general I/O pin. PCR4 is a write-only register. Bits 2 to 0 are always read as 1. 8.2.3 Serial Port Control Register (SPCR) SPCR performs input/output data inversion switching of the RXD32 and TXD32 pins. Figure 8.3 shows the configuration. SCINV2 RXD32 P41/RXD32 SCINV3 P42/TXD32 TXD32 Figure 8.3 Input/Output Data Inversion Function Rev. 1.00 Dec. 13, 2007 Page 155 of 380 REJ09B0430-0100 Section 8 I/O Ports Bit 7, 6 5 Bit Name SPC32 Initial Value All 1 0 R/W R/W Description Reserved These bits are always read as 1 and cannot be modified. P42/TXD32 Pin Function Switch This bit selects whether pin P42/TXD32 is used as P42 or as TXD32. 0: P42 I/O pin 1: TXD32 output pin* Note: * Set the TE bit in SCR3 after setting this bit to 1. 4 3 SCINV3 0 W R/W Reserved The write value should always be 0. TXD32 Pin Output Data Inversion Switch This bit selects whether or not the logic level of the TXD32 pin output data is inverted. 0: TXD32 output data is not inverted 1: TXD32 output data is inverted 2 SCINV2 0 R/W RXD32 Pin Input Data Inversion Switch This bit selects whether or not the logic level of the RXD32 pin input data is inverted. 0: RXD32 input data is not inverted 1: RXD32 input data is inverted 1, 0 W Reserved The write value should always be 0. Note: When the serial port control register is modified, the data being input or output up to that point is inverted immediately after the modification, and an invalid data change is input or output. When modifying the serial port control register, modification must be made in a state in which data changes are invalidated. Rev. 1.00 Dec. 13, 2007 Page 156 of 380 REJ09B0430-0100 Section 8 I/O Ports 8.2.4 Pin Functions The port 4 pin functions are shown below. * P43/IRQ0 pin The pin function depends on the IRQ0 bit in PMR2. IRQ0 Pin Function 0 P43 input pin 1 IRQ0 input pin * P42/TXD32 pin The pin function depends on the combination of bit TE in SCR3, bit SPC32 in SPCR, and bit PCR42 in PCR4. SPC32 TE PCR42 Pin Function [Legend] x: Don't care. 0 P42 input pin 0 0 1 P42 output pin 1 x x TXD32 output pin * P41/RXD32 pin The pin function depends on the combination of bit RE in SCR3 and bit PCR41 in PCR4. RE PCR41 Pin Function [Legend] x: Don't care. 0 P41 input pin 0 1 P41 output pin 1 x RXD32 input pin Rev. 1.00 Dec. 13, 2007 Page 157 of 380 REJ09B0430-0100 Section 8 I/O Ports * P40/SCK32 pin The pin function depends on the combination of bits CKE1 and CKE0 in SCR3, bit COM in SMR, and bit PCR40 in PCR4. CKE1 CKE0 COM PCR40 Pin Function [Legend] x: Don't care. 0 P40 input pin 0 1 P40 output pin 0 1 x SCK32 output pin 0 1 x 1 x x x SCK32 input pin 8.3 Port 5 Port 5 is an I/O port also functioning as a wakeup interrupt request input pin. Figure 8.4 shows its pin configuration. P57/WKP7 P56/WKP6 P55/WKP5 Port 5 P54/WKP4 P53/WKP3 P52/WKP2 P51/WKP1 P50/WKP0 Figure 8.4 Port 5 Pin Configuration Port 5 has the following registers. * * * * Port data register 5 (PDR5) Port control register 5 (PCR5) Port pull-up control register 5 (PUCR5) Port mode register 5 (PMR5) Rev. 1.00 Dec. 13, 2007 Page 158 of 380 REJ09B0430-0100 Section 8 I/O Ports 8.3.1 Port Data Register 5 (PDR5) PDR5 is a register that stores data of port 5. Bit 7 6 5 4 3 2 1 0 Bit Name P57 P56 P55 P54 P53 P52 P51 P50 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description If port 5 is read while PCR5 bits are set to 1, the values stored in PDR5 are read, regardless of the actual pin states. If port 5 is read while PCR5 bits are cleared to 0, the pin states are read. 8.3.2 Port Control Register 5 (PCR5) PCR5 controls whether each of the port 5 pins functions as an input pin or output pin. Bit 7 6 5 4 3 2 1 0 Bit Name PCR57 PCR56 PCR55 PCR54 PCR53 PCR52 PCR51 PCR50 Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description Setting a PCR5 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. The settings in PCR5 and in PDR5 are valid only when the corresponding pin is designated by PMR5 and the SGS3 to SGS0 bits in LPCR as a general I/O pin. PCR5 is a write-only register. Bits 7 to 0 are always read as 1. Rev. 1.00 Dec. 13, 2007 Page 159 of 380 REJ09B0430-0100 Section 8 I/O Ports 8.3.3 Port Pull-Up Control Register 5 (PUCR5) PUCR5 controls whether the pull-up MOS of each of the port 5 pins is on or off. Bit 7 6 5 4 3 2 1 0 Bit Name PUCR57 PUCR56 PUCR55 PUCR54 PUCR53 PUCR52 PUCR51 PUCR50 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description When a PCR5 bit is cleared to 0, setting the corresponding PUCR5 bit to 1 turns on the pull-up MOS for the corresponding pin, while clearing the bit to 0 turns off the pull-up MOS. 8.3.4 Port Mode Register 5 (PMR5) PMR5 controls the selection of pin functions for port 5 pins. Bit 7 6 5 4 3 2 1 0 Bit Name WKP7 WKP6 WKP5 WKP4 WKP3 WKP2 WKP1 WKP0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description P5n/WKPn Pin Function Switch These bits select whether pin P5n/WKPn is used as P5n or WKPn. 0: P5n I/O pin 1: WKPn input pin (n = 7 to 0) Rev. 1.00 Dec. 13, 2007 Page 160 of 380 REJ09B0430-0100 Section 8 I/O Ports 8.3.5 Pin Functions The port 5 pin functions are shown below. * P57/WKP7 to P54/WKP4 pins The pin function depends on the combination of bit WKPn in PMR5 and bit PCR5n in PCR5. (n = 7 to 4) WKPn PCR5n Pin Function [Legend] x: Don't care. 0 P5n input pin 0 1 P5n output pin 1 x WKPn input pin * P53/WKP3 to P50/WKP0 pins The pin function depends on the combination of bit WKPm in PMR5 and bit PCR5m in PCR5. (m = 3 to 0) WKPm PCR5m Pin Function [Legend] x: Don't care. 0 P5m input pin 0 1 P5m output pin 1 x WKPm input pin Rev. 1.00 Dec. 13, 2007 Page 161 of 380 REJ09B0430-0100 Section 8 I/O Ports 8.3.6 Input Pull-Up MOS Port 5 has an on-chip input pull-up MOS function that can be controlled by software. When the PCR5 bit is cleared to 0, setting the corresponding PUCR5 bit to 1 turns on the input pull-up MOS for that pin. The input pull-up MOS function is in the off state after a reset. (n = 7 to 0) PCR5n PUCR5n Input Pull-Up MOS [Legend] x: Don't care. 0 Off 0 1 On 1 x Off 8.4 Port 6 Port 6 is an I/O port. Figure 8.5 shows its pin configuration. P67 P66 P65 Port 6 P64 P63 P62 P61 P60 Figure 8.5 Port 6 Pin Configuration Port 6 has the following registers. * Port data register 6 (PDR6) * Port control register 6 (PCR6) * Port pull-up control register 6 (PUCR6) Rev. 1.00 Dec. 13, 2007 Page 162 of 380 REJ09B0430-0100 Section 8 I/O Ports 8.4.1 Port Data Register 6 (PDR6) PDR6 is a register that stores data of port 6. Bit 7 6 5 4 3 2 1 0 Bit Name P67 P66 P65 P64 P63 P62 P61 P60 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description If port 6 is read while PCR6 bits are set to 1, the values stored in PDR6 are read, regardless of the actual pin states. If port 6 is read while PCR6 bits are cleared to 0, the pin states are read. 8.4.2 Port Control Register 6 (PCR6) PCR6 controls whether each of the port 6 pins functions as an input pin or output pin. Bit 7 6 5 4 3 2 1 0 Bit Name PCR67 PCR66 PCR65 PCR64 PCR63 PCR62 PCR61 PCR60 Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description Setting a PCR6 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. PCR6 is a write-only register. Bits 7 to 0 are always read as 1. Rev. 1.00 Dec. 13, 2007 Page 163 of 380 REJ09B0430-0100 Section 8 I/O Ports 8.4.3 Port Pull-Up Control Register 6 (PUCR6) PUCR6 controls whether the pull-up MOS of each of the port 6 pins is on or off. Bit 7 6 5 4 3 2 1 0 Bit Name PUCR67 PUCR66 PUCR65 PUCR64 PUCR63 PUCR62 PUCR61 PUCR60 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description When a PCR6 bit is cleared to 0, setting the corresponding PUCR6 bit to 1 turns on the pull-up MOS for the corresponding pin, while clearing the bit to 0 turns off the pull-up MOS. 8.4.4 Pin Functions The port 6 pin functions are shown below. * P67 to P64 pins The pin function depends on the setting of bit PCR6n in PCR6. (n = 7 to 4) PCR6n Pin Function 0 P6n input pin 1 P6n output pin * P63 to P60 pins The pin function depends on the setting of bit PCR6m in PCR6. (m = 3 to 0) PCR6m Pin Function 0 P6m input pin 1 P6m output pin Rev. 1.00 Dec. 13, 2007 Page 164 of 380 REJ09B0430-0100 Section 8 I/O Ports 8.4.5 Input Pull-Up MOS Port 6 has an on-chip input pull-up MOS function that can be controlled by software. When the PCR6 bit is cleared to 0, setting the corresponding PUCR6 bit to 1 turns on the input pull-up MOS for that pin. The input pull-up MOS function is in the off state after a reset. (n = 7 to 0) PCR6n PUCR6n Input Pull-Up MOS [Legend] x: Don't care. 0 Off 0 1 On 1 x Off 8.5 Port 7 Port 7 is an I/O port. Figure 8.6 shows its pin configuration. P77 P76 P75 Port 7 P74 P73 P72 P71 P70 Figure 8.6 Port 7 Pin Configuration Port 7 has the following registers. * Port data register 7 (PDR7) * Port control register 7 (PCR7) Rev. 1.00 Dec. 13, 2007 Page 165 of 380 REJ09B0430-0100 Section 8 I/O Ports 8.5.1 Port Data Register 7 (PDR7) PDR7 is a register that stores data of port 7. Bit 7 6 5 4 3 2 1 0 Bit Name P77 P76 P75 P74 P73 P72 P71 P70 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description If port 7 is read while PCR7 bits are set to 1, the values stored in PDR7 are read, regardless of the actual pin states. If port 7 is read while PCR7 bits are cleared to 0, the pin states are read. 8.5.2 Port Control Register 7 (PCR7) PCR7 controls whether each of the port 7 pins functions as an input pin or output pin. Bit 7 6 5 4 3 2 1 0 Bit Name PCR77 PCR76 PCR75 PCR74 PCR73 PCR72 PCR71 PCR70 Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description Setting a PCR7 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. The settings in PCR7 and in PDR7 are valid only when the corresponding pin is designated by the SGS3 to SGS0 bits in LPCR as a general I/O pin. PCR7 is a write-only register. Bits 7 to 0 are always read as 1. Rev. 1.00 Dec. 13, 2007 Page 166 of 380 REJ09B0430-0100 Section 8 I/O Ports 8.5.3 Pin Functions The port 7 pin functions are shown below. * P77 to P74 pins The pin function depends on the setting of bit PCR7n in PCR7. (n = 7 to 4) PCR7n Pin Function 0 P7n input pin 1 P7n output pin * P73 to P70 pins The pin function depends on the setting of bit PCR7m in PCR7. (m = 3 to 0) PCR7m Pin Function 0 P7m input pin 1 P7m output pin 8.6 Port 8 Port 8 is an I/O port. Figure 8.7 shows its pin configuration. Port 8 P80 Figure 8.7 Port 8 Pin Configuration Port 8 has the following registers. * Port data register 8 (PDR8) * Port control register 8 (PCR8) Rev. 1.00 Dec. 13, 2007 Page 167 of 380 REJ09B0430-0100 Section 8 I/O Ports 8.6.1 Port Data Register 8 (PDR8) PDR8 is a register that stores data of port 8. Bit 7 to 1 0 Bit Name P80 Initial Value 0 R/W R/W Description Reserved If port 8 is read while PCR8 bits are set to 1, the values stored in PDR8 are read, regardless of the actual pin states. If port 8 is read while PCR8 bits are cleared to 0, the pin states are read. 8.6.2 Port Control Register 8 (PCR8) PCR8 controls whether each of the port 8 pins functions as an input pin or output pin. Bit 7 to 1 0 Bit Name PCR80 Initial Value 0 R/W W W Description Reserved The write value should always be 0. Setting a PCR8 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. PCR8 is a write-only register. 8.6.3 Pin Functions The port 8 pin functions are shown below. * P80 The pin function depends on the setting of bit PCR80 in PCR8. PCR80 Pin Function 0 P80 input pin 1 P80 output pin Rev. 1.00 Dec. 13, 2007 Page 168 of 380 REJ09B0430-0100 Section 8 I/O Ports 8.7 Port 9 Port 9 is a dedicated current port for NMOS output that also functions as a PWM output pin. Figure 8.8 shows its pin configuration. P95 P94 P93 Port 9 P92 P91/PWM2 P90/PWM1 Figure 8.8 Port 9 Pin Configuration Port 9 has the following registers. * Port data register 9 (PDR9) * Port mode register 9 (PMR9) 8.7.1 Port Data Register 9 (PDR9) PDR9 is a register that stores data of port 9. Bit 7, 6 5 4 3 2 1 0 Bit Name P95 P94 P93 P92 P91 P90 Initial Value All 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W Description Reserved The initial value should not be changed. If PDR9 is read, the values stored in PDR9 are read. Rev. 1.00 Dec. 13, 2007 Page 169 of 380 REJ09B0430-0100 Section 8 I/O Ports 8.7.2 Port Mode Register 9 (PMR9) PMR9 controls the selection of the P90 and P91 pin functions. Bit 7 to 4 3 2 1 0 Bit Name PWM2 PWM1 Initial Value All 1 0 0 0 R/W R/W W R/W R/W Description Reserved The initial value should not be changed. Reserved This bit can be read from or written to. Reserved The write value should always be 0. P9n/PWMn+1 Pin Function Switch These bits select whether pin P9n/PWMn+1 is used as P9n or as PWMn+1. (n = 1, 0) 0: P9n output pin 1: PWMn+1 output pin 8.7.3 Pin Functions The port 9 pin functions are shown below. * P91/PWMn+1 to P90/PWMn+1 pins (n = 1, 0) PMR9n Pin Function 0 P9n output pin 1 PWMn+1 output pin Rev. 1.00 Dec. 13, 2007 Page 170 of 380 REJ09B0430-0100 Section 8 I/O Ports 8.8 Port A Port A is an I/O port. Figure 8.9 shows its pin configuration. PA3 Port A PA2 PA1 PA0 Figure 8.9 Port A Pin Configuration Port A has the following registers. * Port data register A (PDRA) * Port control register A (PCRA) 8.8.1 Port Data Register A (PDRA) PDRA is a register that stores data of port A. Bit 7 to 4 3 2 1 0 Bit Name PA3 PA2 PA1 PA0 Initial Value All 1 0 0 0 0 R/W R/W R/W R/W R/W Description Reserved The initial value should not be changed. If port A is read while PCRA bits are set to 1, the values stored in PDRA are read, regardless of the actual pin states. If port A is read while PCRA bits are cleared to 0, the pin states are read. Rev. 1.00 Dec. 13, 2007 Page 171 of 380 REJ09B0430-0100 Section 8 I/O Ports 8.8.2 Port Control Register A (PCRA) PCRA controls whether each of the port A pins functions as an input pin or output pin. Bit 7 to 4 3 2 1 0 Bit Name PCRA3 PCRA2 PCRA1 PCRA0 Initial Value All 1 0 0 0 0 R/W W W W W Description Reserved The initial value should not be changed. Setting a PCRA bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. The settings in PCRA and in PDRA are valid only when the corresponding pin is designated in LPCR as a general I/O pin. PCRA is a write-only register. Bits 3 to 0 are always read as 1. 8.8.3 Pin Functions The port A pin functions are shown below. * PA3 pin The pin function depends on the setting of bit PCRA3 in PCRA. PCRA3 Pin Function 0 PA3 input pin 1 PA3 output pin * PA2 pin The pin function depends on the setting of bit PCRA2 in PCRA. PCRA2 Pin Function 0 PA2 input pin 1 PA2 output pin * PA1 pin The pin function depends on the setting of bit PCRA1 in PCRA. PCRA1 Pin Function 0 PA1 input pin 1 PA1 output pin Rev. 1.00 Dec. 13, 2007 Page 172 of 380 REJ09B0430-0100 Section 8 I/O Ports * PA0 pin The pin function depends on the setting of bit PCRA0 in PCRA. PCRA0 Pin Function 0 PA0 input pin 1 PA0 output pin 8.9 Port B Port B is an input-only port also functioning as an analog input pin and interrupt input pin. Figure 8.10 shows its pin configuration. PB3/AN3/IRQ1 Port B PB2/AN2 PB1/AN1 PB0/AN0 Figure 8.10 Port B Pin Configuration Port B has the following registers. * Port data register B (PDRB) * Port mode register B (PMRB) Rev. 1.00 Dec. 13, 2007 Page 173 of 380 REJ09B0430-0100 Section 8 I/O Ports 8.9.1 Port Data Register B (PDRB) PDRB is a register that stores data of port B. Bit 7 to 4 3 2 1 0 Bit Name PB3 PB2 PB1 PB0 Initial Value R/W Description Reserved Reading PDRB always gives the pin states. However, if a port B pin is selected as an analog input channel for the A/D converter by bits CH3 to CH0 in AMR, that pin reads 0 regardless of the input voltage. Undefined Undefined R R R R 8.9.2 Port Mode Register B (PMRB) PMRB controls the selection of the PB3 pin functions. Bit 7 to 4 Bit Name Initial Value All 1 R/W Description Reserved These bits are always read as 1 and cannot be modified. 3 IRQ1 0 R/W PB3/AN3/IRQ1 Pin Function Switch This bit selects whether pin PB3/AN3/IRQ1 is used as PB3/AN3 or as IRQ1. 0: PB3/AN3 input pin 1: IRQ1 input pin 2 to 0 All 1 Reserved These bits are always read as 1 and cannot be modified. Rev. 1.00 Dec. 13, 2007 Page 174 of 380 REJ09B0430-0100 Section 8 I/O Ports 8.9.3 Pin Functions The port B pin functions are shown below. * PB3/AN3/IRQ1 pin The pin function depends on the combination of bits CH3 to CH0 in AMR and bit IRQ1 in PMRB. IRQ1 CH3 to CH0 Pin Function [Legend] x: Don't care. Other than B'0111 PB3 input pin 0 B'0111 AN3 input pin 1 x IRQ1 input pin * PB2/AN2 pin The pin function depends on bits CH3 to CH0 in AMR. CH3 to CH0 Pin Function Other than B'0110 PB2 input pin B'0110 AN2 input pin * PB1/AN1 pin Switching is accomplished by combining CH3 to CH0 in AMR as shown below. CH3 to CH0 Pin Function Other than B'0101 PB1 input pin B'0101 AN1 input pin * PB0/AN0 pin Switching is accomplished by combining CH3 to CH0 in AMR as shown below. CH3 to CH0 Pin Function Other than B'0100 PB0 input pin B'0100 AN0 input pin Rev. 1.00 Dec. 13, 2007 Page 175 of 380 REJ09B0430-0100 Section 8 I/O Ports 8.10 8.10.1 Usage Notes How to Handle Unused Pin If an I/O pin not used by the user system is floating, pull it up or down. * If an unused pin is an input pin, handle it in one of the following ways: Pull it up to Vcc with an on-chip pull-up MOS. Pull it up to Vcc with an external resistor of approximately 100 k. Pull it down to Vss with an external resistor of approximately 100 k. For a pin also used by the A/D converter, pull it up to AVcc. * If an unused pin is an output pin, handle it in one of the following ways: Set the output of the unused pin to high and pull it up to Vcc with an external resistor of approximately 100 k. Set the output of the unused pin to low and pull it down to GND with an external resistor of approximately 100 k. Rev. 1.00 Dec. 13, 2007 Page 176 of 380 REJ09B0430-0100 Section 9 Timers Section 9 Timers 9.1 Overview This LSI has four timers: timer A, timer F, asynchronous event counter, and watchdog timer. The functions of these timers are summarized in table 9.1. Table 9.1 Name Timer A Timer Functions Functions * * * 8-bit timer Interval function Clock time base Internal Clock /8 to /8192 (8 choices) W/128 (choice of 4 overflow periods) /4 to /32, W/4 -- (4 choices) TMOFL TMOFH Event Input Waveform Pin Output Pin -- -- Remarks Timer F * * 16-bit timer Also usable as two independent 8-bit timers. Output compare output function 16-bit counter Also usable as two independent 8-bit counters Counts events asynchronous to and W Can count asynchronous events (rising/falling/both edges) independently of the MCU's internal clock * Asynchronous event counter (AEC) * * /2 to /8 (3 choices) AEVL AEVH IRQAEC -- * * Watchdog timer * /8192, W/32 Generates a reset signal by overflow of 8-bit counter Rev. 1.00 Dec. 13, 2007 Page 177 of 380 REJ09B0430-0100 Section 9 Timers 9.2 Timer A The timer A is an 8-bit timer with interval timing and realtime clock time-base functions. The clock time-base function is available when a 32.768kHz crystal oscillator is connected. Figure 9.1 shows a block diagram of the timer A. 9.2.1 Features * The timer A can be used as an interval timer or a clock time base. * An interrupt is requested when the counter overflows. * Use of module standby mode enables this module to be placed in standby mode independently when not used. (For details, refer to section 5.4, Module Standby Function.) (1) Interval Timer Choice of eight internal clock sources (/8192, /4096, /2048, /512, /256, /128, /32, and 8) (2) Clock Time Base Choice of four overflow periods (1 s, 0.5 s, 0.25 s, and 31.25 ms) when timer A is used as a clock time base (using a 32.768 kHz crystal oscillator) Rev. 1.00 Dec. 13, 2007 Page 178 of 380 REJ09B0430-0100 Section 9 Timers W 1/4 W/4 PSW TMA W/128 TCA /8192, /4096, /2048, /512, /256, /128, /32, /8 /128* PSS /256* /64* /8* IRRTA [Legend] TMA: Timer mode register A TCA: Timer counter A IRRTA: Timer A overflow interrupt request flag PSW: Prescaler W PSS: Prescaler S Note: * Can be selected only when the prescaler W output (W/128) is used as the TCA input clock. Figure 9.1 Block Diagram of Timer A 9.2.2 Register Descriptions The timer A has the following registers. * Timer mode register A (TMA) * Timer counter A (TCA) Rev. 1.00 Dec. 13, 2007 Page 179 of 380 REJ09B0430-0100 Internal data bus Section 9 Timers (1) Timer Mode Register A (TMA) TMA selects the operating mode, the divided clock output, and the input clock. Bit 7 6 5 4 3 Bit Name TMA3 Initial Value 1 0 R/W W W W R/W Reserved This bit is always read as 1. Internal Clock Select 3 Selects the operating mode of the timer A. 0: Functions as an interval timer to count the outputs of prescaler S. 1: Functions as a clock-time base to count the outputs of prescaler W. 2 1 0 TMA2 TMA1 TMA0 0 0 0 R/W R/W R/W Internal Clock Select 2 to 0 Select the clock input to TCA when TMA3 = 0. 000: /8192 001: /4096 010: /2048 011: /512 100: /256 101: /128 110: /32 111: /8 These bits select the overflow period when TMA3 = 1 (when a 32.768 kHz crystal oscillator is used as w). 000: 1 s 001: 0.5 s 010: 0.25 s 011: 0.03125 s 1xx: Both PSW and TCA are reset [Legend] x: Don't care. Description Reserved The write value should always be 0. Rev. 1.00 Dec. 13, 2007 Page 180 of 380 REJ09B0430-0100 Section 9 Timers (2) Timer Counter A (TCA) TCA is an 8-bit readable up-counter, which is incremented by internal clock input. The clock source for input to this counter is selected by bits TMA3 to TMA0 in TMA. TCA values can be read by the CPU in active mode, but cannot be read in subactive mode. When TCA overflows, the IRRTA bit in the interrupt request register 1 (IRR1) is set to 1. TCA is cleared by setting bits TMA3 and TMA2 in TMA to B'11. TCA is initialized to H'00. 9.2.3 (1) Operation Interval Timer Operation When bit TMA3 in TMA is cleared to 0, the timer A functions as an 8-bit interval timer. Upon reset, TCA is cleared to H'00 and bit TMA3 is cleared to 0, so up-counting of the timer A resume immediately as an interval timer. The clock input to timer A is selected by bits TMA2 to TMA0 in TMA; any of eight internal clock signals output by prescaler S can be selected. After the count value in TCA reaches H'FF, the next clock signal input causes timer A to overflow, setting bit IRRTA to 1 in interrupt Flag Register 1 (IRR1). If IENTA = 1 in the interrupt enable register 1 (IENR1), a CPU interrupt is requested. At overflow, TCA returns to H'00 and starts counting up again. In this mode the timer A functions as an interval timer that generates an overflow output at intervals of 256 input clock pulses. (2) Clock Time Base Operation When bit TMA3 in TMA is set to 1, the timer A functions as a clock-timer base by counting clock signals output by prescaler W. The overflow period of timer A is set by bits TMA1 and TMA0 in TMA. A choice of four periods is available. In clock time base operation (TMA3 = 1), setting bit TMA2 to 1 clears both TCA and prescaler W to H'00. Rev. 1.00 Dec. 13, 2007 Page 181 of 380 REJ09B0430-0100 Section 9 Timers 9.2.4 Timer A Operating States Table 9.2 summarizes the timer A operating states. Table 9.2 Timer A Operating States Reset Reset Active Functions Functions* Functions Sleep Functions Functions* Retained Watch Halted Functions Retained Sub-active Sub-sleep Halted Functions Functions Halted Functions Retained Standby Halted Halted Retained Module Standby Halted Halted Retained Operating Mode TCA Interval Clock Reset time base TMA Reset Note: * When the clock time base function is selected as the internal clock of TCA in active mode or sleep mode, the internal clock is not synchronous with the system clock, so it is synchronized by a synchronizing circuit. This may result in a maximum error of 1/ (s) in the count cycle. 9.3 Timer F The timer F has a 16-bit timer having an output compare function. The timer F also provides for counter resetting, interrupt request generation, toggle output, etc., using compare match signals. Thus, it can be applied to various systems. The timer F can also be used as two independent 8-bit timers (timer FH and timer FL). Figure 9.2 shows a block diagram of the timer F. 9.3.1 Features * Choice of four internal clock sources (/32, /16, /4, and W/4) * Toggle output function Toggle output is performed to the TMOFH pin (TMOFL pin) using a single compare match signal. The initial value of toggle output can be set. * Counter resetting by a compare match signal * Two interrupt sources: One compare match, one overflow * Choice of 16-bit or 8-bit mode by settings of bits CKSH2 to CKSH0 in TCRF * Can operate in watch mode, subactive mode, and subsleep mode When W/4 is selected as an internal clock, the timer F can operate in watch mode, subactive mode, and subsleep mode. * Use of module standby mode enables this module to be placed in standby mode independently when not used. (For details, refer to section 5.4, Module Standby Function.) Rev. 1.00 Dec. 13, 2007 Page 182 of 380 REJ09B0430-0100 Section 9 Timers PSS IRRTFL TCRF W/4 Toggle circuit TCFL TMOFL Comparator OCRFL TCFH Toggle circuit TMOFH Comparator Match OCRFH TCSRF [Legend] TCRF: TCFH: TCFL: Timer control register F 8-bit timer counter FH 8-bit timer counter FL TCSRF: Timer control status register F IRRTFH OCRFH: Output compare register FH OCRFL: Output compare register FL IRRTFH: Timer FH interrupt request flag IRRTFL: Timer FL interrupt request flag PSS: Prescaler S Figure 9.2 Block Diagram of Timer F Rev. 1.00 Dec. 13, 2007 Page 183 of 380 REJ09B0430-0100 Internal data bus Section 9 Timers 9.3.2 Input/Output Pins Table 9.3 shows the pin configuration of the timer F. Table 9.3 Name Timer FH output Timer FL output Pin Configuration Abbreviation I/O TMOFH TMOFL Output Output Function Timer FH toggle output pin Timer FL toggle output pin 9.3.3 Register Descriptions The timer F has the following registers. * * * * (1) Timer counters FH and FL (TCFH,TCFL) Output compare registers FH and FL (OCRFH, OCRFL) Timer control register F (TCRF) Timer control status register F (TCSRF) Timer Counters FH and FL (TCFH, TCFL) TCF is a 16-bit read/write up-counter configured by cascaded connection of 8-bit timer counters TCFH and TCFL. In addition to the use of TCF as a 16-bit counter with TCFH as the upper 8 bits and TCFL as the lower 8 bits, TCFH and TCFL can also be used as independent 8-bit counters. TCFH and TCFL can be read and written by the CPU, but when they are used in 16-bit mode, data transfer to and from the CPU is performed via a temporary register (TEMP). For details of TEMP, see section 9.3.4, CPU Interface. TCFH and TCFL are initialized to H'00 upon reset. (a) 16-bit mode (TCF) When CKSH2 is cleared to 0 in TCRF, TCF operates as a 16-bit counter. The TCF input clock is selected by bits CKSL2 to CKSL0 in TCRF. TCF can be cleared in the event of a compare match by means of CCLRH in TCSRF. When TCF overflows from H'FFFF to H'0000, OVFH is set to 1 in TCSRF. If OVIEH in TCSRF is 1 at this time, IRRTFH is set to 1 in IRR2, and if IENTFH in IENR2 is 1, an interrupt request is sent to the CPU. Rev. 1.00 Dec. 13, 2007 Page 184 of 380 REJ09B0430-0100 Section 9 Timers (b) 8-bit mode (TCFL/TCFH) When CKSH2 is set to 1 in TCRF, TCFH and TCFL operate as two independent 8-bit counters. The TCFH (TCFL) input clock is selected by bits CKSH2 to CKSH0 (CKSL2 to CKSL0) in TCRF. TCFH (TCFL) can be cleared in the event of a compare match by means of CCLRH (CCLRL) in TCSRF. When TCFH (TCFL) overflows from H'FF to H'00, OVFH (OVFL) is set to 1 in TCSRF. If OVIEH (OVIEL) in TCSRF is 1 at this time, IRRTFH (IRRTFL) is set to 1 in IRR2, and if IENTFH (IENTFL) in IENR2 is 1, an interrupt request is sent to the CPU. (2) Output Compare Registers FH and FL (OCRFH, OCRFL) OCRF is a 16-bit read/write register composed of the two registers OCRFH and OCRFL. In addition to the use of OCRF as a 16-bit register with OCRFH as the upper 8 bits and OCRFL as the lower 8 bits, OCRFH and OCRFL can also be used as independent 8-bit registers. OCRFH and OCRFL can be read and written by the CPU, but when they are used in 16-bit mode, data transfer to and from the CPU is performed via a temporary register (TEMP). For details of TEMP, see section 9.3.4, CPU Interface. OCRFH and OCRFL are initialized to H'FF upon reset. (a) 16-bit mode (OCRF) When CKSH2 is cleared to 0 in TCRF, OCRF operates as a 16-bit register. OCRF contents are constantly compared with TCF, and when both values match, CMFH is set to 1 in TCSRF. At the same time, IRRTFH is set to 1 in IRR2. If IENTFH in IENR2 is 1 at this time, an interrupt request is sent to the CPU. Toggle output can be provided from the TMOFH pin by means of compare matches, and the output level can be set (high or low) by means of TOLH in TCRF. (b) 8-bit mode (OCRFH/OCRFL) When CKSH2 is set to 1 in TCRF, OCRFH and OCRFL operate as two independent 8-bit registers. OCRFH contents are compared with TCFH, and OCRFL contents are with TCFL. When the OCRFH (OCRFL) and TCFH (TCFL) values match, CMFH (CMFL) is set to 1 in TCSRF. At the same time, IRRTFH (IRRTFL) is set to 1 in IRR2. If IENTFH (IENTFL) in IENR2 is 1 at this time, an interrupt request is sent to the CPU. Toggle output can be provided from the TMOFH pin (TMOFL pin) by means of compare matches, and the output level can be set (high or low) by means of TOLH (TOLL) in TCRF. Rev. 1.00 Dec. 13, 2007 Page 185 of 380 REJ09B0430-0100 Section 9 Timers (3) Timer Control Register F (TCRF) TCRF switches between 16-bit mode and 8-bit mode, selects the input clock from among four internal clock sources, and sets the output level of the TMOFH and TMOFL pins. Bit 7 Bit Name TOLH Initial Value 0 R/W W Description Toggle Output Level H Sets the TMOFH pin output level. 0: Low level 1: High level Clock Select H Select the clock input to TCFH from among four internal clock sources or TCFL overflow. 000: 16-bit mode, counting on TCFL overflow signal 001: 16-bit mode, counting on TCFL overflow signal 010: 16-bit mode, counting on TCFL overflow signal 011: Using prohibited 100: Internal clock: counting on /32 101: Internal clock: counting on /16 110: Internal clock: counting on /4 111: Internal clock: counting on W/4 Toggle Output Level L Sets the TMOFL pin output level. 0: Low level 1: High level 2 1 0 CKSL2 CKSL1 CKSL0 0 0 0 W W W Clock Select L Select the clock input to TCFL from among four internal clock sources or external event input. 000: Non-operational 001: Using prohibited 010: Using prohibited 011: Using prohibited 100: Internal clock: counting on /32 101: Internal clock: counting on /16 110: Internal clock: counting on /4 111: Internal clock: counting on W/4 6 5 4 CKSH2 CKSH1 CKSH0 0 0 0 W W W 3 TOLL 0 W Rev. 1.00 Dec. 13, 2007 Page 186 of 380 REJ09B0430-0100 Section 9 Timers (4) Timer Control Status Register F (TCSRF) TCSRF performs counter clear selection, overflow flag setting, and compare match flag setting, and controls enabling of overflow interrupt requests. Bit 7 Bit Name OVFH Initial Value 0 R/W R/W* Description Timer Overflow Flag H [Setting condition] When TCFH overflows from H'FF to H'00 [Clearing condition] When this bit is written to 0 after reading OVFH = 1 6 CMFH 0 R/W* Compare Match Flag H This is a status flag indicating that TCFH has matched OCRFH. [Setting condition] When the TCFH value matches the OCRFH value [Clearing condition] When this bit is written to 0 after reading CMFH = 1 5 OVIEH 0 R/W Timer Overflow Interrupt Enable H Selects enabling or disabling of interrupt generation when TCFH overflows. 0: TCFH overflow interrupt request is disabled 1: TCFH overflow interrupt request is enabled 4 CCLRH 0 R/W Counter Clear H In 16-bit mode, this bit selects whether TCF is cleared when TCF and OCRF match. In 8-bit mode, this bit selects whether TCFH is cleared when TCFH and OCRFH match. In 16-bit mode: 0: TCF clearing by compare match is disabled 1: TCF clearing by compare match is enabled In 8-bit mode: 0: TCFH clearing by compare match is disabled 1: TCFH clearing by compare match is enabled Rev. 1.00 Dec. 13, 2007 Page 187 of 380 REJ09B0430-0100 Section 9 Timers Bit 3 Bit Name OVFL Initial Value 0 R/W R/W* Description Timer Overflow Flag L This is a status flag indicating that TCFL has overflowed. [Setting condition] When TCFL overflows from H'FF to H'00 [Clearing condition] When this bit is written to 0 after reading OVFL = 1 2 CMFL 0 R/W* Compare Match Flag L This is a status flag indicating that TCFL has matched OCRFL. [Setting condition] When the TCFL value matches the OCRFL value [Clearing condition] When this bit is written to 0 after reading CMFL = 1 1 OVIEL 0 R/W Timer Overflow Interrupt Enable L Selects enabling or disabling of interrupt generation when TCFL overflows. 0: TCFL overflow interrupt request is disabled 1: TCFL overflow interrupt request is enabled 0 CCLRL 0 R/W Counter Clear L Selects whether TCFL is cleared when TCFL and OCRFL match. 0: TCFL clearing by compare match is disabled 1: TCFL clearing by compare match is enabled Note: * Only 0 can be written to clear the flag. 9.3.4 CPU Interface TCF and OCRF are 16-bit readable/writable registers, but the CPU is connected to the on-chip peripheral modules by an 8-bit data bus. When the CPU accesses these registers, it therefore uses an 8-bit temporary register (TEMP). When performing TCF read/write access or OCRF write access in 16-bit mode, data will not be transferred correctly if only the upper byte or only the lower byte is accessed. Access must be performed for all 16 bits (using two consecutive byte-size MOV instructions), and the upper byte must be accessed before the lower byte. Rev. 1.00 Dec. 13, 2007 Page 188 of 380 REJ09B0430-0100 Section 9 Timers In 8-bit mode, there are no restrictions on the order of access. (1) Write Access Write access to the upper byte results in transfer of the upper-byte write data to TEMP. Next, write access to the lower byte results in transfer of the data in TEMP to the upper register byte, and direct transfer of the lower-byte write data to the lower register byte. Figure 9.3 shows an example in which H'AA55 is written to TCF. Write to upper byte Module data bus CPU [H'AA] Bus interface TEMP [H'AA] TCFH [ ] TCFL [ ] Write to lower byte Module data bus CPU [H'55] Bus interface TEMP [H'AA] TCFH [H'AA] TCFL [H'55] Figure 9.3 Write Access to TCF (CPU TCF) Rev. 1.00 Dec. 13, 2007 Page 189 of 380 REJ09B0430-0100 Section 9 Timers (2) Read Access In access to TCF, when the upper byte is read the upper-byte data is transferred directly to the CPU and the lower-byte data is transferred to TEMP. Next, when the lower byte is read, the lower-byte data in TEMP is transferred to the CPU. In access to OCRF, when the upper byte is read the upper-byte data is transferred directly to the CPU. When the lower byte is read, the lower-byte data is transferred directly to the CPU. Figure 9.4 shows an example in which TCF is read when it contains H'AAFF. Read upper byte Module data bus CPU [H'AA] Bus interface TEMP [H'FF] TCFH [H'AA] TCFL [H'FF] Read lower byte Module data bus CPU [H'FF] Bus interface TEMP [H'FF] TCFH [AB] * Note: H'AB00 if counter has been updated once. TCFL [00] * Figure 9.4 Read Access to TCF (TCF CPU) Rev. 1.00 Dec. 13, 2007 Page 190 of 380 REJ09B0430-0100 Section 9 Timers 9.3.5 Operation The timer F is a 16-bit counter that increments on each input clock pulse. The timer F value is constantly compared with the value set in the output compare register F, and the counter can be cleared, an interrupt requested, or port output toggled, when the two values match. The timer F can also function as two independent 8-bit timers. (1) Timer F Operation The timer F has two operating modes, 16-bit timer mode and 8-bit timer mode. The operation in each of these modes is described below. (a) Operation in 16-bit timer mode When CKSH2 is cleared to 0 in timer control register F (TCRF), timer F operates as a 16-bit timer. The timer F operating clock can be selected from three internal clocks output by prescaler S by means of bits CKSL2 to CKSL0 in TCRF. OCRF contents are constantly compared with TCF, and when both values match, CMFH is set to 1 in TCSRF. If IENTFH in IENR2 is 1 at this time, an interrupt request is sent to the CPU, and at the same time, TMOFH pin output is toggled. If CCLRH in TCSRF is 1, TCF is cleared. TMOFH pin output can also be set by TOLH in TCRF. When TCF overflows from H'FFFF to H'0000, OVFH is set to 1 in TCSRF. If OVIEH in TCSRF and IENTFH in IENR2 are both 1, an interrupt request is sent to the CPU. (b) Operation in 8-bit timer mode When CKSH2 is set to 1 in TCRF, TCF operates as two independent 8-bit timers, TCFH and TCFL. The TCFH/TCFL input clock is selected by CKSH2 to CKSH0/CKSL2 to CKSL0 in TCRF. When the OCRFH/OCRFL and TCFH/TCFL values match, CMFH/CMFL is set to 1 in TCSRF. If IENTFH/IENTFL in IENR2 is 1, an interrupt request is sent to the CPU, and at the same time, TMOFH pin/TMOFL pin output is toggled. If CCLRH/CCLRL in TCSRF is 1, TCFH/TCFL is cleared. TMOFH pin/TMOFL pin output can also be set by TOLH/TOLL in TCRF. When TCFH/TCFL overflows from H'FF to H'00, OVFH/OVFL is set to 1 in TCSRF. If OVIEH/OVIEL in TCSRF and IENTFH/IENTFL in IENR2 are both 1, an interrupt request is sent to the CPU. Rev. 1.00 Dec. 13, 2007 Page 191 of 380 REJ09B0430-0100 Section 9 Timers (2) TCF Increment Timing TCF is incremented by clock input (internal clock input). Bits CKSH2 to CKSH0 or CKSL2 to CKSL0 in TCRF select one of four internal clock sources (/32, /16, /4, or W/4) created by dividing the system clock ( or W). (3) TMOFH/TMOFL Output Timing In TMOFH/TMOFL output, the value set in TOLH/TOLL in TCRF is output. The output is toggled by the occurrence of a compare match. Figure 9.5 shows the output timing. Count input clock TCF N N+1 N N+1 OCRF N N Compare match signal TMOFH, TMOFL Figure 9.5 TMOFH/TMOFL Output Timing (4) TCF Clear Timing TCF can be cleared by a compare match with OCRF. (5) Timer Overflow Flag (OVF) Set Timing OVF is set to 1 when TCF overflows from H'FFFF to H'0000. Rev. 1.00 Dec. 13, 2007 Page 192 of 380 REJ09B0430-0100 Section 9 Timers (6) Compare Match Flag Set Timing The compare match flag (CMFH or CMFL) is set to 1 when the TCF and OCRF values match. The compare match signal is generated in the last state during which the values match (when TCF is updated from the matching value to a new value). When TCF matches OCRF, the compare match signal is not generated until the next counter clock. 9.3.6 Timer F Operating States The timer F operating states are shown in table 9.4. Table 9.4 Operating Mode TCF Timer F Operating States Reset Reset Active Functions* Sleep Functions* Watch Functions/ Halted* Retained Retained Retained Sub-active Sub-sleep Standby Functions/ Halted* Functions Functions Functions Functions/ Halted* Retained Retained Retained Halted Module Standby Halted OCRF TCRF TCSRF Reset Reset Reset Functions Functions Functions Retained Retained Retained Retained Retained Retained Retained Retained Retained Note: * When W/4 is selected as the TCF internal clock in active mode or sleep mode, since the system clock and internal clock are mutually asynchronous, synchronization is maintained by a synchronization circuit. This results in a maximum count cycle error of 1/ (s). When the counter is operated in subactive mode, watch mode, or subsleep mode, W /4 must be selected as the internal clock. The counter will not operate if any other internal clock is selected. Rev. 1.00 Dec. 13, 2007 Page 193 of 380 REJ09B0430-0100 Section 9 Timers 9.3.7 Usage Notes The following types of contention and operation can occur when the timer F is used. (1) 16-Bit Timer Mode In toggle output, TMOFH pin output is toggled when all 16 bits match and a compare match signal is generated. If a TCRF write by a MOV instruction and generation of the compare match signal occur simultaneously, TOLH data is output to the TMOFH pin as a result of the TCRF write. TMOFL pin output is unstable in 16-bit mode, and should not be used; the TMOFL pin should be used as a port pin. If an OCRFL write and compare match signal generation occur simultaneously, the compare match signal is invalid. However, even if the written data and the counter value match, a compare match signal is not necessarily generated at that point. As the compare match signal is output in synchronization with the TCFL clock, a compare match will not result in compare match signal generation if the clock is stopped. Compare match flag CMFH is set when all 16 bits match and a compare match signal is generated. Compare match flag CMFL is set if the setting conditions for the lower 8 bits are satisfied. When TCF overflows, OVFH is set. OVFL is set if the setting conditions are satisfied when the lower 8 bits overflow. If a TCFL write and overflow signal output occur simultaneously, the overflow signal is not output. (2) (a) 8-Bit Timer Mode: TCFH, OCRFH In toggle output, TMOFH pin output is toggled when a compare match occurs. If a TCRF write by a MOV instruction and generation of the compare match signal occur simultaneously, TOLH data is output to the TMOFH pin as a result of the TCRF write. If an OCRFH write and compare match signal generation occur simultaneously, the compare match signal is invalid. However, even if the written data and the counter value match, a compare match signal is not necessarily generated at that point. The compare match signal is output in synchronization with the TCFH clock. If a TCFH write and overflow signal output occur simultaneously, the overflow signal is not output. Rev. 1.00 Dec. 13, 2007 Page 194 of 380 REJ09B0430-0100 Section 9 Timers (b) TCFL, OCRFL In toggle output, TMOFL pin output is toggled when a compare match occurs. If a TCRF write by a MOV instruction and generation of the compare match signal occur simultaneously, TOLL data is output to the TMOFL pin as a result of the TCRF write. If an OCRFL write and compare match signal generation occur simultaneously, the compare match signal is invalid. However, even if the written data and the counter value match, a compare match signal is not necessarily generated at that point. As the compare match signal is output in synchronization with the TCFL clock, a compare match will not result in compare match signal generation if the clock is stopped. If a TCFL write and overflow signal output occur simultaneously, the overflow signal is not output. (3) Clear Timer FH, Timer FL Interrupt Request Flags (IRRTFH, IRRTFL), Timer Overflow Flags H, L (OVFH, OVFL), and Compare Match Flags H, L (CMFH, CMFL) When W/4 is selected as the internal clock, "Interrupt source generation signal" will be operated with W and the signal will be outputted with W width. And, "Overflow signal" and "Compare match signal" are controlled with 2 cycles of W signals. Those signals are outputted with 2 cycles width of W (figure 9.6) In active (high-speed, medium-speed) mode, even if you cleared interrupt request flag during the term of validity of "Interrupt source generation signal", same interrupt request flag is set. (1 in figure 9.6) And, the timer overflow flag and compare match flag cannot be cleared during the term of validity of "Overflow signal" and "Compare match signal". For interrupt request flag is set right after interrupt request is cleared, interrupt process to one time timer FH, timer FL interrupt might be repeated. (2 in figure 9.6) Therefore, to definitely clear interrupt request flag in active (high-speed, medium-speed) mode, clear should be processed after the time that calculated with below (1) formula. And, to definitely clear timer overflow flag and compare match flag, clear should be processed after read timer control status register F (TCSRF) after the time that calculated with below (1) formula. For ST of (1) formula, please substitute the longest number of execution states in used instruction. (10 states of RTE instruction when MULXU, DIVXU instruction is not used, 14 states when MULXU, DIVXU instruction is used) Rev. 1.00 Dec. 13, 2007 Page 195 of 380 REJ09B0430-0100 Section 9 Timers In subactive mode, there are not limitation for interrupt request flag, timer overflow flag, and compare match flag clear. The term of validity of "Interrupt source generation signal" = 1 cycle of W + waiting time for completion of executing instruction + interrupt time synchronized with = 1/W + ST x (1/) + (2/) (second).....(1) ST: Executing number of execution states Method 1 is recommended to operate for time efficiency. Method 1 1. Prohibit interrupt in interrupt handling routine (set IENFH, IENFL to 0). 2. After program process returned normal handling, clear interrupt request flags (IRRTFH, IRRTFL) after more than that calculated with (1) formula. 3. After reading the timer control status register F (TCSRF), clear the timer overflow flags (OVFH, OVFL) and compare match flags (CMFH, CMFL). 4. Enable interrupts (set IENFH, IENFL to 1). Method 2 1. Set interrupt handling routine time to more than time that calculated with (1) formula. 2. Clear interrupt request flags (IRRTFH, IRRTFL) at the end of interrupt handling routine. 3. After read timer control status register F (TCSRF), clear timer overflow flags (OVFH, OVFL) and compare match flags (CMFH, CMFL). All above attentions are also applied in 16-bit mode and 8-bit mode. Rev. 1.00 Dec. 13, 2007 Page 196 of 380 REJ09B0430-0100 Section 9 Timers Interrupt request flag clear 2 Program processing Interrupt Interrupt request flag clear Interrupt Normal w Interrupt source generation signal (internal signal, nega-active) Overflow signal, compare match signal (internal signal, nega-active) Interrupt request flag (IRRTFH, IRRTFL) 1 Figure 9.6 Clear Interrupt Request Flag when Interrupt Source Generation Signal is Valid (4) Timer Counter (TCF) Read/Write When W/4 is selected as the internal clock in active (high-speed, medium-speed) mode, write on TCF is impossible. And when reading TCF, as the system clock and internal clock are mutually asynchronous, TCF synchronizes with synchronization circuit. This results in a maximum TCF read value error of 1. When reading or writing TCF in active (high-speed, medium-speed) mode is needed, please select the internal clock except for W/4 before read/write is performed. In subactive mode, even if W /4 is selected as the internal clock, TCF can be read from or written to normally. Rev. 1.00 Dec. 13, 2007 Page 197 of 380 REJ09B0430-0100 Section 9 Timers 9.4 Asynchronous Event Counter (AEC) The asynchronous event counter is incremented by external event clock or internal clock input. Figure 9.7 shows a block diagram of the asynchronous event counter. 9.4.1 Features * Can count asynchronous events Can count external events input asynchronously without regard to the operation of system clocks and SUB * Can be used as two-channel independent 8-bit event counter or single-channel independent 16bit event counter. * Event/clock input is enabled only when IRQAEC is high or event counter PWM output (IECPWM) is high. * Both edge sensing can be used for IRQAEC or event counter PWM output (IECPWM) interrupts. When the asynchronous counter is not used, they can be used as independent interrupts. * When an event counter PWM is used, event clock input enabling/disabling can be controlled automatically in a fixed cycle. * External event input or a prescaler output clock can be selected by software for the ECH and ECL clock sources. /2, /4, or /8 can be selected as the prescaler output clock. * Both edge counting is possible for AEVL and AEVH. * Counter resetting and halting of the count-up function can be controlled by software * Automatic interrupt generation on detection of an event counter overflow * Use of module standby mode enables this module to be placed in standby mode independently when not used. (For details, refer to section 5.4, Module Standby Function.) Rev. 1.00 Dec. 13, 2007 Page 198 of 380 REJ09B0430-0100 Section 9 Timers IRREC PSS ECCR ECCSR /2 /4, /8 ECH (8 bits) OVH AEVH Edge sensing circuit OVL CK CK AEVL IRQAEC Edge sensing circuit Edge sensing circuit To CPU interrupt (IRREC2) ECPWCRL ECPWCRH IECPWM PWM waveform generator /2, /4, /8, /16, /32, /64 ECPWDRL ECPWDRH AEGSR [Legend] ECPWCRH: ECPWDRH: AEGSR: ECCSR: ECL: Event counter PWM compare register H Event counter PWM data register H Input pin edge select register Event counter control/status register Event counter L ECPWCRL: ECPWDRL: ECCR: ECH: Event counter PWM compare register L Event counter PWM data register L Event counter control register Event counter H Figure 9.7 Block Diagram of Asynchronous Event Counter Rev. 1.00 Dec. 13, 2007 Page 199 of 380 REJ09B0430-0100 Internal data bus ECL (8 bits) Section 9 Timers 9.4.2 Input/Output Pins Table 9.5 shows the pin configuration of the asynchronous event counter. Table 9.5 Name Pin Configuration Abbreviation I/O Input Input Input Function Event input pin for input to event counter H Event input pin for input to event counter L Input pin for interrupt enabling event input Asynchronous event input H AEVH Asynchronous event input L Event input enable interrupt input AEVL IRQAEC 9.4.3 Register Descriptions The asynchronous event counter has the following registers. * * * * * * * * * Event counter PWM compare register H (ECPWCRH) Event counter PWM compare register L (ECPWCRL) Event counter PWM data register H (ECPWDRH) Event counter PWM data register L (ECPWDRL) Input pin edge select register (AEGSR) Event counter control register (ECCR) Event counter control/status register (ECCSR) Event counter H (ECH) Event counter L (ECL) Rev. 1.00 Dec. 13, 2007 Page 200 of 380 REJ09B0430-0100 Section 9 Timers (1) Event Counter PWM Compare Register H (ECPWCRH) ECPWCRH sets the one conversion period of the event counter PWM waveform. Bit 7 6 5 4 3 2 1 0 Bit Name ECPWCRH7 ECPWCRH6 ECPWCRH5 ECPWCRH4 ECPWCRH3 ECPWCRH2 ECPWCRH1 ECPWCRH0 Initial Value 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description One conversion period of event counter PWM waveform Notes: When ECPWME in AEGSR is 1, the event counter PWM is operating and therefore ECPWCRH should not be modified. When changing the conversion period, the event counter PWM must be halted by clearing ECPWME to 0 in AEGSR before modifying ECPWCRH. (2) Event Counter PWM Compare Register L (ECPWCRL) ECPWCRL sets the one conversion period of the event counter PWM waveform. Bit 7 6 5 4 3 2 1 0 Bit Name ECPWCRL7 ECPWCRL6 ECPWCRL5 ECPWCRL4 ECPWCRL3 ECPWCRL2 ECPWCRL1 ECPWCRL0 Initial Value 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description One conversion period of event counter PWM waveform Notes: When ECPWME in AEGSR is 1, the event counter PWM is operating and therefore ECPWCRL should not be modified. When changing the conversion period, the event counter PWM must be halted by clearing ECPWME to 0 in AEGSR before modifying ECPWCRL. Rev. 1.00 Dec. 13, 2007 Page 201 of 380 REJ09B0430-0100 Section 9 Timers (3) Event Counter PWM Data Register H (ECPWDRH) ECPWDRH controls data of the event counter PWM waveform generator. Bit 7 6 5 4 3 2 1 0 Bit Name ECPWDRH7 ECPWDRH6 ECPWDRH5 ECPWDRH4 ECPWDRH3 ECPWDRH2 ECPWDRH1 ECPWDRH0 Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description Data control of event counter PWM waveform generator Notes: When ECPWME in AEGSR is 1, the event counter PWM is operating and therefore ECPWDRH should not be modified. When changing the data, the event counter PWM must be halted by clearing ECPWME to 0 in AEGSR before modifying ECPWDRH. (4) Event Counter PWM Data Register L (ECPWDRL) ECPWDRL controls data of the event counter PWM waveform generator. Bit 7 6 5 4 3 2 1 0 Bit Name ECPWDRL7 ECPWDRL6 ECPWDRL5 ECPWDRL4 ECPWDRL3 ECPWDRL2 ECPWDRL1 ECPWDRL0 Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description Data control of event counter PWM waveform generator Notes: When ECPWME in AEGSR is 1, the event counter PWM is operating and therefore ECPWDRL should not be modified. When changing the data, the event counter PWM must be halted by clearing ECPWME to 0 in AEGSR before modifying ECPWDRL. Rev. 1.00 Dec. 13, 2007 Page 202 of 380 REJ09B0430-0100 Section 9 Timers (5) Input Pin Edge Select Register (AEGSR) AEGSR selects rising, falling, or both edge sensing for the AEVH, AEVL, and IRQAEC pins. Bit 7 6 Bit Name AHEGS1 AHEGS0 Initial Value 0 0 R/W R/W R/W Description AEC Edge Select H Select rising, falling, or both edge sensing for the AEVH pin. 00: Falling edge on AEVH pin is sensed 01: Rising edge on AEVH pin is sensed 10: Both edges on AEVH pin are sensed 11: Setting prohibited 5 4 ALEGS1 ALEGS0 0 0 R/W R/W AEC Edge Select L Select rising, falling, or both edge sensing for the AEVL pin. 00: Falling edge on AEVL pin is sensed 01: Rising edge on AEVL pin is sensed 10: Both edges on AEVL pin are sensed 11: Setting prohibited 3 2 AIEGS1 AIEGS0 0 0 R/W R/W IRQAEC Edge Select Select rising, falling, or both edge sensing for the IRQAEC pin. 00: Falling edge on IRQAEC pin is sensed 01: Rising edge on IRQAEC pin is sensed 10: Both edges on IRQAEC pin are sensed 11: Setting prohibited 1 ECPWME 0 R/W Event Counter PWM Enable Controls operation of event counter PWM and selection of IRQAEC. 0: AEC PWM halted, IRQAEC selected 1: AEC PWM enabled, IRQAEC not selected 0 0 R/W Reserved This bit can be read from or written to. However, this bit should not be set to 1. Rev. 1.00 Dec. 13, 2007 Page 203 of 380 REJ09B0430-0100 Section 9 Timers (6) Event Counter Control Register (ECCR) ECCR controls the counter input clock and IRQAEC/IECPWM. Bit 7 6 Bit Name ACKH1 ACKH0 Initial Value 0 0 R/W R/W R/W Description AEC Clock Select H Select the clock used by ECH. 00: AEVH pin input 01: /2 10: /4 11: /8 5 4 ACKL1 ACKL0 0 0 R/W R/W AEC Clock Select L Select the clock used by ECL. 00: AEVL pin input 01: /2 10: /4 11: /8 3 2 1 PWCK2 PWCK1 PWCK0 0 0 0 R/W R/W R/W Event Counter PWM Clock Select Select the event counter PWM clock. 000: /2 001: /4 010: /8 011: /16 1x0: /32 1x1 /64 0 0 R/W Reserved This bit can be read from or written to. However, this bit should not be set to 1. [Legend] x: Don't care. Rev. 1.00 Dec. 13, 2007 Page 204 of 380 REJ09B0430-0100 Section 9 Timers (7) Event Counter Control/Status Register (ECCSR) ECCSR controls counter overflow detection, counter clear resetting, and the count-up function. Bit 7 Bit Name OVH Initial Value 0 R/W R/W* Description Counter Overflow H This is a status flag indicating that ECH has overflowed. [Setting condition] When ECH overflows from H'FF to H'00 [Clearing condition] When this bit is written to 0 after reading OVH = 1 6 OVL 0 R/W* Counter Overflow L This is a status flag indicating that ECL has overflowed. [Setting condition] When ECL overflows from H'FF to H'00 [Clearing condition] When this bit is written to 0 after reading OVL = 1 5 0 R/W Reserved This bit can be read from or written to. However, the initial value should not be changed. 4 CH2 0 R/W Channel Select Selects how ECH and ECL event counters are used 0: ECH and ECL are used together as a single-channel 16bit event counter 1: ECH and ECL are used as two-channel 8-bit event counter 3 CUEH 0 R/W Count-Up Enable H Enables event clock input to ECH. 0: ECH event clock input is disabled (ECH value is retained) 1: ECH event clock input is enabled 2 CUEL 0 R/W Count-Up Enable L Enables event clock input to ECL. 0: ECL event clock input is disabled (ECL value is retained) 1: ECL event clock input is enabled Rev. 1.00 Dec. 13, 2007 Page 205 of 380 REJ09B0430-0100 Section 9 Timers Bit 1 Bit Name CRCH Initial Value 0 R/W R/W Description Counter Reset Control H Controls resetting of ECH. 0: ECH is reset 1: ECH reset is cleared and count-up function is enabled 0 CRCL 0 R/W Counter Reset Control L Controls resetting of ECL. 0: ECL is reset 1: ECL reset is cleared and count-up function is enabled Note: * Only 0 can be written to clear the flag. (8) Event Counter H (ECH) ECH is an 8-bit read-only up-counter that operates as an independent 8-bit event counter. ECH also operates as the upper 8-bit up-counter of a 16-bit event counter configured in combination with ECL. Bit 7 6 5 4 3 2 1 0 Bit Name ECH7 ECH6 ECH5 ECH4 ECH3 ECH2 ECH1 ECH0 Initial Value 0 0 0 0 0 0 0 0 R/W R R R R R R R R Description Either the external asynchronous event AEVH pin, /2, /4, or /8, or the overflow signal from lower 8-bit counter ECL can be selected as the input clock source. ECH can be cleared by clearing the CRC bits in ECCSR to 0. Rev. 1.00 Dec. 13, 2007 Page 206 of 380 REJ09B0430-0100 Section 9 Timers (9) Event Counter L (ECL) ECL is an 8-bit read-only up-counter that operates as an independent 8-bit event counter. ECL also operates as the lower 8-bit up-counter of a 16-bit event counter configured in combination with ECH. Bit 7 6 5 4 3 2 1 0 Bit Name ECL7 ECL6 ECL5 ECL4 ECL3 ECL2 ECL1 ECL0 Initial Value 0 0 0 0 0 0 0 0 R/W R R R R R R R R Description Either the external asynchronous event AEVL pin, /2, /4, or /8 can be selected as the input clock source. ECL can be cleared by clearing the CRCL bit in ECCSR to 0. 9.4.4 (1) Operation 16-Bit Counter Operation When bit CH2 is cleared to 0 in ECCSR, ECH and ECL operate as a 16-bit event counter. Any of four input clock sources--/2, /4, /8, or AEVL pin input--can be selected by means of bits ACKL1 and ACKL0 in ECCR. When AEVL pin input is selected, input sensing is selected with bits ALEGS1 and ALEGS0. The input clock is enabled only when IRQAEC is high or IECPWM is high. When IRQAEC is low or IECPWM is low, the input clock is not input to the counter, which therefore does not operate. Figure 9.8 shows an example of the software processing when ECH and ECL are used as a 16-bit event counter. Rev. 1.00 Dec. 13, 2007 Page 207 of 380 REJ09B0430-0100 Section 9 Timers Start Clear CH2 to 0 Set ACKL1, ACKL0, ALEGS1, and ALEGS0 Clear CUEH, CUEL, CRCH, and CRCL to 0 Clear OVH and OVL to 0 Set CUEH, CUEL, CRCH, and CRCL to 1 End Figure 9.8 Example of Software Processing when Using ECH and ECL as 16-Bit Event Counter As CH2 is cleared to 0 by a reset, ECH and ECL operate as a 16-bit event counter after a reset, and as ACKL1 and ACKL0 are cleared to B00, the operating clock is asynchronous event input from the AEVL pin (using falling edge sensing). When the next clock is input after the count value reaches H'FF in both ECH and ECL, ECH and ECL overflow from H'FFFF to H'0000, the OVH flag is set to 1 in ECCSR, the ECH and ECL count values each return to H'00, and counting up is restarted. When overflow occurs, the IRREC bit is set to 1 in IRR2. If the IENEC bit in IENR2 is 1 at this time, an interrupt request is sent to the CPU. (2) 8-Bit Counter Operation When bit CH2 is set to 1 in ECCSR, ECH and ECL operate as independent 8-bit event counters. /2, /4, /8, or AEVH pin input can be selected as the input clock source for ECH by means of bits ACKH1 and ACKH0 in ECCR, and /2, /4, /8, or AEVL pin input can be selected as the input clock source for ECL by means of bits ACKL1 and ACKL0 in ECCR. Input sensing is selected with bits AHEGS1 and AHEGS0 when AEVH pin input is selected, and with bits ALEGS1 and ALEGS0 when AEVL pin input is selected. The input clock is enabled only when IRQAEC is high or IECPWM is high. When IRQAEC is low or IECPWM is low, the input clock is not input to the counter, which therefore does not operate. Figure 9.9 shows an example of the software processing when ECH and ECL are used as 8-bit event counters. Rev. 1.00 Dec. 13, 2007 Page 208 of 380 REJ09B0430-0100 Section 9 Timers Start Set CH2 to 1 Set ACKH1, ACKH0, ACKL1, ACKL0, AHEGS1, AHEGS0, ALEGS1, and ALEGS0 Clear CUEH, CUEL, CRCH, and CRCL to 0 Clear OVH and OVL to 0 Set CUEH, CUEL, CRCH, and CRCL to 1 End Figure 9.9 Example of Software Processing when Using ECH and ECL as 8-Bit Event Counters ECH and ECL can be used as 8-bit event counters by carrying out the software processing shown in the example in figure 9.9. When the next clock is input after the ECH count value reaches H'FF, ECH overflows, the OVH flag is set to 1 in ECCSR, the ECH count value returns to H'00, and counting up is restarted. Similarly, when the next clock is input after the ECL count value reaches H'FF, ECL overflows, the OVL flag is set to 1 in ECCSR, the ECL count value returns to H'00, and counting up is restarted. When an overflow occurs, the IRREC bit is set to 1 in IRR2. If the IENEC bit in IENR2 is 1 at this time, an interrupt request is sent to the CPU. (3) IRQAEC Operation When ECPWME in AEGSR is 0, the ECH and ECL input clocks are enabled only when IRQAEC is high. When IRQAEC is low, the input clocks are not input to the counters, and so ECH and ECL do not count. ECH and ECL count operations can therefore be controlled from outside by controlling IRQAEC. In this case, ECH and ECL cannot be controlled individually. IRQAEC can also operate as an interrupt source. In this case the vector number is 6 and the vector addresses are H'000C and H'000D. Interrupt enabling is controlled by IENEC2 in IENR1. When an IRQAEC interrupt is generated, IRR1 interrupt request flag IRREC2 is set to 1. If IENEC2 in IENR1 is set to 1 at this time, an interrupt request is sent to the CPU. Rising, falling, or both edge sensing can be selected for the IRQAEC input pin with bits AIAGS1 and AIAGS0 in AEGSR. Rev. 1.00 Dec. 13, 2007 Page 209 of 380 REJ09B0430-0100 Section 9 Timers (4) Event Counter PWM Operation When ECPWME in AEGSR is 1, the ECH and ECL input clocks are enabled only when event counter PWM output (IECPWM) is high. When IECPWM is low, the input clocks are not input to the counters, and so ECH and ECL do not count. ECH and ECL count operations can therefore be controlled cyclically from outside by controlling event counter PWM. In this case, ECH and ECL cannot be controlled individually. IECPWM can also operate as an interrupt source. In this case the vector number is 6 and the vector addresses are H'000C and H'000D. Interrupt enabling is controlled by IENEC2 in IENR1. When an IECPWM interrupt is generated, IRR1 interrupt request flag IRREC2 is set to 1. If IENEC2 in IENR1 is set to 1 at this time, an interrupt request is sent to the CPU. Rising, falling, or both edge detection can be selected for IECPWM interrupt sensing with bits AIAGS1 and AIAGS0 in AEGSR. Figure 9.10 and table 9.6 show examples of event counter PWM operation. [Legend] ton: Clock input enable time toff: Clock input disable time tcm: One conversion period T: ECPWM input clock cycle Ndr: Value of ECPWDRH and ECPWDRL Fixed low when Ndr = H'FFFF Ncm: Value of ECPWCRH and ECPWCRL toff = T * (Ndr +1) ton tcm = T * (Ncm +1) Figure 9.10 Event Counter Operation Waveform Note: Ndr and Ncm above must be set so that Ndr < Ncm. If the settings do not satisfy this condition, do not set ECPWME to 1 in AEGSR. Rev. 1.00 Dec. 13, 2007 Page 210 of 380 REJ09B0430-0100 Section 9 Timers Table 9.6 Examples of Event Counter PWM Operation Conditions: fosc = 4 MHz, f = 2 MHz, high-speed active mode, ECPWCR value (Ncm) = H'7A11, ECPWDR value (Ndr) = H'16E3 Clock Source Selection /2 /4 /8 /16 /32 /64 Note: * Clock Source ECPWMCR ECPWMDR Cycle (T)* Value (Ncm) Value (Ndr) 1 s 2 s 4 s 8 s 16 s 32 s toff minimum width H'7A11 D'31249 H'16E3 D'5859 toff = T x (Ndr + 1) 5.86 ms 11.72 ms 23.44 ms 46.88 ms 93.76 ms 187.52 ms tcm = T x (Ncm + 1) 31.25 ms 62.5 ms 125.0 ms 250.0 ms 500.0 ms 1000.0 ms ton = tcm - toff 25.39 ms 50.78 ms 101.56 ms 203.12 ms 406.24 ms 812.48 ms (5) Clock Input Enable/Disable Function Operation The clock input to the event counter can be controlled by the IRQAEC pin when ECPWME in AEGSR is 0, and by the event counter PWM output, IECPWM when ECPWME in AEGSR is 1. As this function forcibly terminates the clock input by each signal, a maximum error of one count will occur depending on the IRQAEC or IECPWM timing. Figure 9.11 shows an example of the operation of this function. Input event IRQAEC or IECPWM Edge generated by clock return Actually counted clock source Counter value N N+1 N+2 N+3 N+4 N+5 N+6 Clock stopped Figure 9.11 Example of Clock Control Operation Rev. 1.00 Dec. 13, 2007 Page 211 of 380 REJ09B0430-0100 Section 9 Timers 9.4.5 Operating States of Asynchronous Event Counter The operating states of the asynchronous event counter are shown in table 9.7. Table 9.7 Operating Mode AEGSR ECCR ECCSR ECH ECL IRQAEC Operating States of Asynchronous Event Counter Reset Active Reset Reset Reset Reset Reset Reset Functions Functions Functions Functions Functions Functions Functions Sleep Functions Functions Functions Functions Functions Functions Functions Watch Retained*1 Retained* Retained* 1 Subactive Functions Functions Functions Sub-sleep Standby Functions Functions Functions Retained*1 Retained* Retained* 1 Module Standby Retained Retained Retained Halted Halted Retained*4 Retained 1 1 Functions*1*2 Functions*1*2 Retained*3 Retained Functions*2 Functions*2 Functions*1*2 Functions*2 Functions*2 Functions*1*2 Functions Retained Functions Retained Retained*3 Retained Event counter Reset PWM Notes: 1. When an asynchronous external event is input, the counter increments but the counter overflow H/L flags are not affected. 2. Functions when asynchronous external events are selected; halted and retained otherwise. 3. Clock control by IRQAEC operates, but interrupts do not. 4. As the clock is stopped in module standby mode, IRQAEC has no effect. Rev. 1.00 Dec. 13, 2007 Page 212 of 380 REJ09B0430-0100 Section 9 Timers 9.4.6 Usage Notes 1. When reading the values in ECH and ECL, first clear bits CUEH and CUEL to 0 in ECCSR in 8-bit mode and clear bit CUEL to 0 in 16-bit mode to prevent asynchronous event input to the counter. The correct value will not be returned if the event counter increments while being read. 2. The maximum clock frequency that may be input to the AEVH and AEVL pins is either 4MHz with voltage range of 1.8 V to 3.6 V, or 10 MHz with voltage range of 7 V to 3.6 V. For information on the clock high width and low width, see section 14, Electrical Characteristics. The duty ratio does not matter as long as the high width and low width satisfy the minimum requirement. Mode Active (high-speed), sleep (high-speed) Active (medium-speed), sleep (medium-speed) (/16) (/32) (/64) fOSC = 1 MHz to 4 MHz Watch, subactive, subsleep, standby W = 32.768 kHz or 38.4 kHz* 2 Maximum Clock Frequency Input to AEVH/AEVL Pin 10 MHz 2 * fOSC fOSC 1/2 * fOSC 1/4 * fOSC 1000 kHz 500 kHz 250 kHz (/128) (W/2) (W/4) (W/8) 3. When AEC uses with 16-bit mode, set CUEH in ECCSR to 1 first, set CRCH in ECCSR to 1 second, or set both CUEH and CRCH to 1 at same time before clock input. While AEC is operating on 16-bit mode, do not change CUEH. Otherwise, ECH will be miscounted up. 4. When ECPWME in AEGSR is 1, the event counter PWM is operating and therefore ECPWCRH, ECPWCRL, ECPWDRH, and ECPWDRL should not be modified. When changing the data, the event counter PWM must be halted by clearing ECPWME to 0 in AEGSR before modifying these registers. 5. The event counter PWM data register and event counter PWM compare register must be set so that event counter PWM data register < event counter PWM compare register. If the settings do not satisfy this condition, do not set ECPWME to 1 in AEGSR. 6. As synchronization is established internally when an IRQAEC interrupt is generated, a maximum error of 1 tcyc will occur between clock halting and interrupt acceptance. Rev. 1.00 Dec. 13, 2007 Page 213 of 380 REJ09B0430-0100 Section 9 Timers 9.5 Watchdog Timer The watchdog timer is an 8-bit timer that can generate an internal reset signal for this LSI if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. Figure 9.12 shows a block diagram of the watchdog timer. 9.5.1 Features * Selectable from two counter input clocks Two clock sources (/8192 or W/32) can be selected as the timer-counter clock. * Reset signal generated on counter overflow An overflow period of 1 to 256 times the selected clock can be set. * Use of module standby mode enables this module to be placed in standby mode independently when not used. (For details, refer to section 5.4, Module Standby Function.) w/32 TCSRW PSS /8192 TCW [Legend] TCSRW: Timer control/status register W TCW: Timer counter W PSS: Prescaler S Internal reset signal Figure 9.12 Block Diagram of Watchdog Timer Rev. 1.00 Dec. 13, 2007 Page 214 of 380 REJ09B0430-0100 Internal data bus Section 9 Timers 9.5.2 Register Descriptions The watchdog timer has the following registers. * Timer control/status register W (TCSRW) * Timer counter W (TCW) (1) Timer Control/Status Register W (TCSRW) TCSRW performs the TCSRW and TCW write control. TCSRW also controls the watchdog timer operation and indicates the operating state. TCSRW must be rewritten by using the MOV instruction. The bit manipulation instruction cannot be used to change the setting value. Bit 7 Bit Name B6WI Initial Value 1 R/W R Description Bit 6 Write Inhibit The TCWE bit can be written only when the write value of the B6WI bit is 0. 6 TCWE 0 This bit is always read as 1. * Timer Counter W Write Enable R/(W) TCW can be written when the TCWE bit is set to 1. When writing data to this bit, the value for bit 7 must be 0. 5 B4WI 1 R Bit 4 Write Inhibit The TCSRWE bit can be written only when the write value of the B4WI bit is 0. This bit is always read as 1. 4 TCSRWE 0 R/(W)* Timer Control/Status Register W Write Enable The WDON and WRST bits can be written when the TCSRWE bit is set to 1. When writing data to this bit, the value for bit 5 must be 0. 3 B2WI 1 R Bit 2 Write Inhibit This bit can be written to the WDON bit only when the write value of the B2WI bit is 0. This bit is always read as 1. Rev. 1.00 Dec. 13, 2007 Page 215 of 380 REJ09B0430-0100 Section 9 Timers Bit 2 Bit Name WDON Initial Value 0 R/W Description R/(W)* Watchdog Timer On TCW starts counting up when WDON is set to 1 and halts when WDON is cleared to 0. [Setting condition] When 1 is written to the WDON bit while writing 0 to the B2WI bit when the TCSRWE bit=1 [Clearing condition] * * Reset by RES pin When 0 is written to the WDON bit while writing 0 to the B2WI when the TCSRWE bit=1 1 B0WI 1 R Bit 0 Write Inhibit This bit can be written to the WRST bit only when the write value of the B0WI bit is 0. This bit is always read as 1. 0 WRST 0 R/(W)* Watchdog Timer Reset [Setting condition] When TCW overflows and an internal reset signal is generated [Clearing condition] * * Reset by RES pin When 0 is written to the WRST bit while writing 0 to the B0WI bit when the TCSRWE bit = 1 Note: * These bits can be written only when the writing conditions are satisfied. (2) Timer Counter W (TCW) TCW is an 8-bit readable/writable up-counter. When TCW overflows from H'FF to H'00, the internal reset signal is generated and the WRST bit in TCSRW is set to 1. TCW is initialized to H'00. Rev. 1.00 Dec. 13, 2007 Page 216 of 380 REJ09B0430-0100 Section 9 Timers 9.5.3 Operation The watchdog timer is provided with an 8-bit counter. The input clock is selected by the WDCKS bit in the port mode register 2 (PMR2)*: /8192 is selected when the WDCKS bit is cleared to 0, and w/32 when set to 1.. If 1 is written to WDON while writing 0 to B2WI when the TCSRWE bit in TCSRW is set to 1, TCW begins counting up (to operate the watchdog timer, two write accesses to TCSRW are required). When a clock pulse is input after the TCW count value has reached H'FF, the watchdog timer overflows and an internal reset signal is generated. The internal reset signal is output for a period of 512 osc clock cycles. TCW is a writable counter, and when a value is set in TCW, the count-up starts from that value. An overflow period in the range of 1 to 256 input clock cycles can therefore be set, according to the TCW set value. Note: * For details, refer to section 8.1.5, Port Mode Register 2 (PMR2). Figure 9.13 shows an example of watchdog timer operation. Example: With 30-ms overflow period when = 4 MHz 4 x 106 8192 x 30 x 10-3 = 14.6 Therefore, 256 - 15 = 241 (H'F1) is set in TCW. TCW overflow H'FF H'F1 TCW count value H'00 Start H'F1 written to TCW Internal reset signal 512 osc clock cycles H'F1 written to TCW Reset generated Figure 9.13 Example of Watchdog Timer Operation Rev. 1.00 Dec. 13, 2007 Page 217 of 380 REJ09B0430-0100 Section 9 Timers 9.5.4 Operating States of Watchdog Timer Tables 9.8 summarizes the operating states of the watchdog timer. Table 9.8 Operating Mode TCW Operating States of Watchdog Timer Reset Reset Active Functions Sleep Functions Watch Halted Sub-active Sub-sleep Functions/ Halted* Functions/ Halted* Halted Standby Halted Module Standby Halted TCSRW Reset Functions Functions Retained Retained Retained Retained Note: * Functions when W/32 is selected as the input clock. Rev. 1.00 Dec. 13, 2007 Page 218 of 380 REJ09B0430-0100 Section 10 Serial Communication Interface 3 (SCI3) Section 10 Serial Communication Interface 3 (SCI3) Serial Communication Interface 3 (SCI3) can handle both asynchronous and clock synchronous serial communication. In the asynchronous method, serial data communication can be carried out using standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or an Asynchronous Communication Interface Adapter (ACIA). Figure 10.1 shows a block diagram of the SCI3. 10.1 Features * Choice of asynchronous or clock synchronous serial communication mode * Full-duplex communication capability The transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously. Double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data. * On-chip baud rate generator allows any bit rate to be selected * On-chip baud rate generator, internal clock, or external clock can be selected as a transfer clock source. * Six interrupt sources Transmit-end, transmit-data-empty, receive-data-full, overrun error, framing error, and parity error. * Use of module standby mode enables this module to be placed in standby mode independently when it is not in use (for details, see section 5.4, Module Standby Function). Asynchronous mode * * * * * Data length: 7, 8, or 5 bits Stop bit length: 1 or 2 bits Parity: Even, odd, or none Receive error detection: Parity, overrun, and framing errors Break detection: Break can be detected by reading the RXD32 pin level directly in the case of a framing error Rev. 1.00 Dec. 13, 2007 Page 219 of 380 REJ09B0430-0100 Section 10 Serial Communication Interface 3 (SCI3) Clocked synchronous mode * Data length: 8 bits * Receive error detection: Overrun errors detected SCK32 External clock Baud rate generator Internal clock (/64, /16, w/2, ) BRC Clock BRR Transmit/receive control circuit SCR3 SSR TXD32 SPCR RXD32 TSR TDR RSR RDR Interrupt request (TEI, TXI, RXI, ERI) [Legend] Receive shift register RSR: Receive data register RDR: Transmit shift register TSR: Transmit data register TDR: Serial mode register SMR: SCR3: Serial control register 3 Serial status register SSR: Bit rate register BRR: Bit rate counter BRC: SPCR: Serial port control register Figure 10.1 Block Diagram of SCI3 Rev. 1.00 Dec. 13, 2007 Page 220 of 380 REJ09B0430-0100 Internal data bus SMR Section 10 Serial Communication Interface 3 (SCI3) 10.2 Input/Output Pins Table 10.1 shows the SCI3 pin configuration. Table 10.1 Pin Configuration Pin Name SCI3 clock SCI3 receive data input SCI3 transmit data output Abbreviation SCK32 RXD32 TXD32 I/O I/O Input Output Function SCI3 clock input/output SCI3 receive data input SCI3 transmit data output 10.3 Register Descriptions The SCI3 has the following registers. * * * * * * * * * Receive shift register (RSR) Receive data register (RDR) Transmit shift register (TSR) Transmit data register (TDR) Serial mode register (SMR) Serial control register 3 (SCR3) Serial status register (SSR) Bit rate register (BRR) Serial port control register (SPCR) Receive Shift Register (RSR) 10.3.1 RSR is a shift register that is used to receive serial data input from the RXD32 pin and convert it into parallel data. When one byte of data has been received, it is transferred to RDR automatically. RSR cannot be directly accessed by the CPU. Rev. 1.00 Dec. 13, 2007 Page 221 of 380 REJ09B0430-0100 Section 10 Serial Communication Interface 3 (SCI3) 10.3.2 Receive Data Register (RDR) RDR is an 8-bit register that stores received data. When the SCI3 has received one byte of serial data, it transfers the received serial data from RSR to RDR, where it is stored. After this, RSR is receive-enabled. As RSR and RDR function as a double buffer in this way, continuous receive operations are possible. After confirming that the RDRF bit in SSR is set to 1, read RDR only once. RDR cannot be written to by the CPU. RDR is initialized to H'00 at a reset and in standby, watch, or module standby mode. 10.3.3 Transmit Shift Register (TSR) TSR is a shift register that transmits serial data. To perform serial data transmission, the SCI3 first transfers transmit data from TDR to TSR automatically, then sends the data that starts from the LSB to the TXD32 pin. Data transfer from TDR to TSR is not performed if no data has been written to TDR (if the TDRE bit in SSR is set to 1). TSR cannot be directly accessed by the CPU. 10.3.4 Transmit Data Register (TDR) TDR is an 8-bit register that stores data for transmission. When the SCI3 detects that TSR is empty, it transfers the transmit data written in TDR to TSR and starts transmission. The doublebuffered structure of TDR and TSR enables continuous serial transmission. If the next transmit data has already been written to TDR during transmission of one-frame data, the SCI3 transfers the written data to TSR to continue transmission. To achieve reliable serial transmission, write transmit data to TDR only once after confirming that the TDRE bit in SSR is set to 1. TDR is initialized to H'FF at a reset and in standby, watch, or module standby mode. Rev. 1.00 Dec. 13, 2007 Page 222 of 380 REJ09B0430-0100 Section 10 Serial Communication Interface 3 (SCI3) 10.3.5 Serial Mode Register (SMR) SMR is used to set the SCI3's serial transfer format and select the on-chip baud rate generator clock source. SMR is initialized to H'00 at a reset and in standby, watch, or module standby mode. Bit 7 Bit Name COM Initial Value 0 R/W R/W Description Communication Mode 0: Asynchronous mode 1: Clocked synchronous mode 6 CHR 0 R/W Character Length (enabled only in asynchronous mode) 0: Selects 8 or 5 bits as the data length. 1: Selects 7 or 5 bits as the data length. When 7-bit data is selected, the MSB (bit 7) in TDR is not transmitted. To select 5 bits as the data length, set 1 to both the PE and MP bits. The three most significant bits (bits 7, 6, and 5) in TDR are not transmitted. In clock synchronous mode, the data length is fixed to 8 bits regardless of the CHR bit setting. 5 PE 0 R/W Parity Enable (enabled only in asynchronous mode) When this bit is set to 1, the parity bit is added to transmit data before transmission, and the parity bit is checked in reception. In clock synchronous mode, parity bit addition and checking is not performed regardless of the PE bit setting. Rev. 1.00 Dec. 13, 2007 Page 223 of 380 REJ09B0430-0100 Section 10 Serial Communication Interface 3 (SCI3) Bit 4 Bit Name PM Initial Value 0 R/W R/W Description Parity Mode (enabled only when the PE bit is 1 in asynchronous mode) 0: Selects even parity. 1: Selects odd parity. When even parity is selected, a parity bit is added in transmission so that the total number of 1 bits in the transmit data plus the parity bit is an even number; in reception, a check is carried out to confirm that the number of 1 bits in the receive data plus the parity bit is an even number. When odd parity is selected, a parity bit is added in transmission so that the total number of 1 bits in the transmit data plus the parity bit is an odd number; in reception, a check is carried out to confirm that the number of 1 bits in the receive data plus the parity bit is an odd number. If parity bit addition and checking is disabled in clock synchronous mode and asynchronous mode, the PM bit setting is invalid. 3 STOP 0 R/W Stop Bit Length (enabled only in asynchronous mode) Selects the stop bit length in transmission. 0: 1 stop bit 1: 2 stop bits For reception, only the first stop bit is checked, regardless of the value in the bit. If the second stop bit is 0, it is treated as the start bit of the next transmit character. 2 MP 0 R/W Five-Bit Communications When this bit is set to 1, the five-bit communications format is available. When writing 1 to this bit, be sure to write 1 to the PE bit (bit 5 of this register) simultaneously. Rev. 1.00 Dec. 13, 2007 Page 224 of 380 REJ09B0430-0100 Section 10 Serial Communication Interface 3 (SCI3) Bit 1 0 Bit Name CKS1 CKS0 Initial Value 0 0 R/W R/W R/W Description Clock Select 0 and 1 These bits select the clock source for the on-chip baud rate generator. 00: clock (n = 0) 01: w/2 or w clock (n = 1) 10: /16 clock (n = 2) 11: /64 clock (n = 3) When the setting value is 01 in active mode and sleep mode, w/2 clock is set. In subactive mode and subsleep mode, w clock is set. The SCI3 is enabled only when w /2 is selected for the CPU operating clock. For the relationship between the bit rate register setting and the baud rate, see section 10.3.8, Bit Rate Register (BRR). n is the decimal representation of the value of n in BRR (see section 10.3.8, Bit Rate Register (BRR). Rev. 1.00 Dec. 13, 2007 Page 225 of 380 REJ09B0430-0100 Section 10 Serial Communication Interface 3 (SCI3) 10.3.6 Serial Control Register 3 (SCR3) SCR3 is a register that enables or disables SCI3 transfer operations and interrupt requests, and is also used to select the transfer clock source. SCR3 is initialized to H'00 at a reset and in standby, watch, or module standby mode. For details on interrupt requests, refer to section 10.6, Interrupts. Bit 7 Bit Name TIE Initial Value 0 R/W R/W Description Transmit Interrupt Enable When this bit is set to 1, the TXI interrupt request is enabled. TXI can be released by clearing the TDRE bit or TIE bit to 0. 6 RIE 0 R/W Receive Interrupt Enable When this bit is set to 1, RXI and ERI interrupt requests are enabled. RXI and ERI can be released by clearing bit RDRF or the FER, PER, or OER error flag to 0, or by clearing bit RIE to 0. 5 TE 0 R/W Transmit Enable When this bit is set to 1, transmission is enabled. When this bit is 0, the TDRE bit in SSR is fixed at 1. When transmit data is written to TDR while this bit is 1, bit TDRE in SSR is cleared to 0 and serial data transmission is started. Be sure to carry out SMR settings, and setting of bit SPC32 in SPCR, to decide the transmission format before setting bit TE to 1. 4 RE 0 R/W Receive Enable When this bit is set to 1, reception is enabled. In this state, serial data reception is started when a start bit is detected in asynchronous mode or serial clock input is detected in clock synchronous mode. Be sure to carry out the SMR settings to decide the reception format before setting bit RE to 1. Note that the RDRF, FER, PER, and OER flags in SSR are not affected when bit RE is cleared to 0, and retain their previous state. Rev. 1.00 Dec. 13, 2007 Page 226 of 380 REJ09B0430-0100 Section 10 Serial Communication Interface 3 (SCI3) Bit 3 2 Bit Name -- TEIE Initial Value 0 0 R/W R/W R/W Description Reserved Only 0 should be written to this bit. Transmit End Interrupt Enable When this bit is set to 1, the TEI interrupt request is enabled. TEI can be released by clearing bit TDRE to 0 and clearing bit TEND to 0 in SSR, or by clearing bit TEIE to 0. 1 0 CKE1 CKE0 0 0 R/W R/W Clock Enable 0 and 1 Selects the clock source. Asynchronous mode: 00: Internal baud rate generator 01: Internal baud rate generator Outputs a clock of the same frequency as the bit rate from the SCK32 pin. 10: External clock Inputs a clock with a frequency 16 times the bit rate from the SCK32 pin. 11: Reserved Clocked synchronous mode: 00: Internal clock (SCK32 pin functions as clock output) 01: Reserved 10: External clock (SCK32 pin functions as clock input) 11: Reserved Rev. 1.00 Dec. 13, 2007 Page 227 of 380 REJ09B0430-0100 Section 10 Serial Communication Interface 3 (SCI3) 10.3.7 Serial Status Register (SSR) SSR is a register containing status flags of the SCI3 and multiprocessor bits for transfer. 1 cannot be written to flags TDRE, RDRF, OER, PER, and FER; they can only be cleared. SSR is initialized to H'84 at a reset and in standby, watch, or module standby mode. Bit 7 Bit Name TDRE Initial Value 1 R/W Description R/(W)* Transmit Data Register Empty Indicates that transmit data is stored in TDR. [Setting conditions] * * * When the TE bit in SCR3 is 0 When data is transferred from TDR to TSR When 0 is written to TDRE after reading TDRE = 1 [Clearing conditions] * When the transmit data is written to TDR * Receive Data Register Full R/(W) Indicates that the received data is stored in RDR. [Setting condition] * When serial reception ends normally and receive data is transferred from RSR to RDR When 0 is written to RDRF after reading RDRF = 1 When data is read from RDR 6 RDRF 0 [Clearing conditions] * * If an error is detected in reception, or if the RE bit in SCR3 has been cleared to 0, RDR and bit RDRF are not affected and retain their previous state. Note that if data reception is completed while bit RDRF is still set to 1, an overrun error (OER) will occur and the receive data will be lost. Rev. 1.00 Dec. 13, 2007 Page 228 of 380 REJ09B0430-0100 Section 10 Serial Communication Interface 3 (SCI3) Bit 5 Bit Name OER Initial Value 0 R/W Description R/(W)* Overrun Error [Setting condition] * * When an overrun error occurs in reception When 0 is written to OER after reading OER = 1 [Clearing condition] When bit RE in SCR3 is cleared to 0, bit OER is not affected and retains its previous state. When an overrun error occurs, RDR retains the receive data it held before the overrun error occurred, and data received after the error is lost. Reception cannot be continued with bit OER set to 1, and in clock synchronous mode, transmission cannot be continued either. 4 FER 0 R/(W)* Framing Error [Setting condition] * * When a framing error occurs in reception When 0 is written to FER after reading FER = 1 [Clearing condition] When bit RE in SCR3 is cleared to 0, bit FER is not affected and retains its previous state. Note that, in 2-stop-bit mode, only the first stop bit is checked for a value of 1, and the second stop bit is not checked. When a framing error occurs, the receive data is transferred to RDR but bit RDRF is not set. Reception cannot be continued with bit FER set to 1. In clock synchronous mode, neither transmission nor reception is possible when bit FER is set to 1. Rev. 1.00 Dec. 13, 2007 Page 229 of 380 REJ09B0430-0100 Section 10 Serial Communication Interface 3 (SCI3) Bit 3 Bit Name PER Initial Value 0 R/W Description R/(W)* Parity Error [Setting condition] * * When a parity error is generated during reception When 0 is written to PER after reading PER = 1 [Clearing condition] When bit RE in SCR3 is cleared to 0, bit PER is not affected and retains its previous state. Receive data in which a parity error has occurred is still transferred to RDR, but bit RDRF is not set. Reception cannot be continued with bit PER set to 1. In clock synchronous mode, neither transmission nor reception is possible when bit PER is set to 1. 2 TEND 1 R Transmit End [Setting conditions] * * When the TE bit in SCR3 is 0 When TDRE = 1 at transmission of the last bit of a 1byte serial transmit character When 0 is written to TDRE after reading TDRE = 1 When the transmit data is written to TDR [Clearing conditions] * * 1 0 Note: * -- -- 0 0 R R/W Reserved This is a read-only bit and cannot be modified. Reserved The write value should always be 0. Only 0 can be written for clearing a flag. Rev. 1.00 Dec. 13, 2007 Page 230 of 380 REJ09B0430-0100 Section 10 Serial Communication Interface 3 (SCI3) 10.3.8 Bit Rate Register (BRR) BRR is an 8-bit readable/writable register that adjusts the bit rate. BRR is initialized to H'FF at a reset and in standby, watch, or module standby mode. Table 10.2 shows the relationship between the N setting in BRR and the n setting in bits CKS1 and CKS0 of SMR in asynchronous mode. Table 10.4 shows the maximum bit rate for each frequency in asynchronous mode. The values shown in both tables 10.2 and 10.4 are values in active (high-speed) mode. Table 10.5 shows the relationship between the N setting in BRR and the n setting in bits CKS1 and CKS0 in SMR in clock synchronous mode. The values are shown in table 10.5. The N setting in BRR and error for other operating frequencies and bit rates can be obtained by the following formulas: [Asynchronous Mode] N= -1 32 x 22n x B x 100 Error (%) = B (bit rate obtained from n, N, ) - R (bit rate in left-hand column in table 10.2) R (bit rate in left-hand column in table 10.2) Legend: B: N: : n: Bit rate (bit/s) BRR setting for baud rate generator (0 N 255) Operating frequency (Hz) Baud rate generator input clock number (n = 0, 2, or 3) (The relation between n and the clock is shown in table 10.3.) Rev. 1.00 Dec. 13, 2007 Page 231 of 380 REJ09B0430-0100 Section 10 Serial Communication Interface 3 (SCI3) Table 10.2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1) 16.4 kHz Bit Rate (bit/s) 110 150 200 250 300 600 1200 2400 4800 9600 19200 31250 38400 n -- -- -- 0 -- -- N -- -- -- 1 -- -- Error (%) -- -- -- 2.5 -- -- n -- 0 0 -- 0 0 -- 19.45 kHz N -- 3 2 -- 1 0 -- Error (%) -- 0 0 -- 0 0 -- n 2 2 2 3 0 0 0 0 -- -- -- 0 -- 1 MHz N 17 12 9 1 103 51 25 12 -- -- -- 0 -- Error (%) -1.36 0.16 -2.34 -2.34 0.16 0.16 0.16 0.16 -- -- -- 0 -- n 2 3 3 0 3 3 2 2 0 0 0 -- 0 1.2288 MHz N 21 3 2 153 1 0 1 0 7 3 1 -- 0 Error (%) -0.83 0 0 -0.26 0 0 0 0 0 0 0 -- 0 Rev. 1.00 Dec. 13, 2007 Page 232 of 380 REJ09B0430-0100 Section 10 Serial Communication Interface 3 (SCI3) Table 10.2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2) 2 MHz Bit Rate (bit/s) 110 150 200 250 300 600 1200 2400 4800 9600 19200 31250 38400 n 3 2 3 2 2 0 0 0 0 -- -- 0 -- N 8 25 4 15 12 Error (%) -1.36 0.16 -2.34 -2.34 0.16 n 3 3 3 3 3 3 3 3 2 2 0 0 0 5 MHz N 21 15 11 9 7 3 1 0 1 0 7 4 3 Error (%) 0.88 1.73 1.73 -2.34 1.73 1.73 1.73 1.73 1.73 1.73 1.73 0 1.73 n 3 3 3 3 3 2 2 0 0 0 0 0 -- 8 MHz N 35 25 19 15 12 25 12 103 51 25 12 7 -- Error (%) -1.36 0.16 -2.34 -2.34 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0 -- n 3 3 3 3 3 3 3 3 3 2 2 0 0 10 MHz N 43 32 23 19 15 7 3 1 0 1 0 9 7 Error (%) 0.88 -1.36 1.73 -2.34 1.73 1.73 1.73 1.73 1.73 1.73 1.73 0 1.73 103 0.16 51 25 12 -- -- 1 -- 0.16 0.16 0.16 -- -- 0 -- [Legend] No indication: Setting not possible. : A setting is available but error occurs Table 10.3 Relation between n and Clock SMR Setting n 0 0 2 3 Clock W/2*1/W*2 /16 /64 CKS1 0 0 1 1 CKS0 0 1 0 1 Notes: 1. W/2 clock in active (medium-speed/high-speed) mode and sleep (medium-speed/highspeed) mode 2. W clock in subactive mode and subsleep mode In subactive or subsleep mode, the SCI3 can be operated when CPU clock is W/2 only. Rev. 1.00 Dec. 13, 2007 Page 233 of 380 REJ09B0430-0100 Section 10 Serial Communication Interface 3 (SCI3) Table 10.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode) Setting OSC (MHz) 0.0384* 2 2.4576 4 10 16 20 Note: * (MHz) 0.0192 1 1.2288 2 5 8 10 Maximum Bit Rate (bit/s) 600 31250 38400 62500 156250 250000 312500 n 0 0 0 0 0 0 0 N 0 0 0 0 0 0 0 When CKS1 = 0 and CKS0 = 1 in SMR Table 10.5 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) (1) 19.2 kHz Bit Rate (bit/s) 200 250 300 500 1k 2.5k 5k 10k 25k 50k 100k 250k 500k 1M n 0 -- 2 N 23 -- 0 Error (%) 0 -- 0 n -- -- -- -- 0 0 0 0 0 0 -- 0 1 MHz N -- -- -- -- 249 99 49 24 9 4 -- 0 Error (%) -- -- -- -- 0 0 0 0 0 0 -- 0 n -- 2 -- -- -- 0 0 0 0 0 0 0 0 2 MHz N -- 124 -- -- -- 199 99 49 19 9 4 1 0 Error (%) -- 0 -- -- -- 0 0 0 0 0 0 0 0 Rev. 1.00 Dec. 13, 2007 Page 234 of 380 REJ09B0430-0100 Section 10 Serial Communication Interface 3 (SCI3) Table 10.5 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) (2) Bit Rate (bit/s) 200 250 300 500 1k 2.5k 5k 10k 25k 50k 100k 250k 500k 1M 5 MHz n -- -- -- -- -- -- 0 0 0 0 -- 0 -- -- N -- -- -- -- -- -- 249 124 49 24 -- 4 -- -- Error (%) -- -- -- -- -- -- 0 0 0 0 -- 0 -- -- n -- 3 -- 2 2 2 2 0 0 0 0 0 0 0 8 MHz N -- 124 -- 249 124 49 24 199 79 39 19 7 3 1 Error (%) -- 0 -- 0 0 0 0 0 0 0 0 0 0 0 n 0 2 0 0 0 0 0 0 0 0 0 0 0 -- N 12499 624 8332 4999 2499 999 499 249 99 49 24 9 4 -- 10 MHz Error (%) 0 0 0 0 0 0 0 0 0 0 0 0 0 -- [Legend] Blankx: No setting is available. --: A setting is available but error occurs. Note: The value set in BRR is given by the following formula: N= -1 8 x 22n x B B: N: : n: Bit rate (bit/s) BRR setting for baud rate generator (0 N 255) Operating frequency (Hz) Baud rate generator input clock number (n = 0, 2, or 3) (The relation between n and the clock is shown in table 10.6.) Rev. 1.00 Dec. 13, 2007 Page 235 of 380 REJ09B0430-0100 Section 10 Serial Communication Interface 3 (SCI3) Table 10.6 Relation between n and Clock SMR Setting n 0 0 2 3 Clock W/2*1/W*2 /16 /64 CKS1 0 0 1 1 CKS0 0 1 0 1 Notes: 1. W/2 clock in active (medium-speed/high-speed) mode and sleep (medium-speed/highspeed) mode 2. W clock in subactive mode and subsleep mode In subactive or subsleep mode, the SCI3 can be operated when CPU clock is W/2 only. Rev. 1.00 Dec. 13, 2007 Page 236 of 380 REJ09B0430-0100 Section 10 Serial Communication Interface 3 (SCI3) 10.3.9 Serial Port Control Register (SPCR) SPCR selects whether input/output data of the RXD32 and TXD32 pins is inverted or not. Bit 7, 6 5 Bit Name SPC32 Initial Value All 1 0 R/W R/W Description Reserved These bits are always read as 1 and cannot be modified. P42/TXD32 Pin Function Switch This bit selects whether pin P42/TXD32 is used as P42 or as TXD32. 0: P42 I/O pin 1: TXD32 output pin* Note: * Set the TE bit in SCR3 after setting this bit to 1. 4 3 SCINV3 0 W R/W Reserved The write value should always be 0. TXD32 Pin Output Data Inversion Switch This bit selects whether or not the logic level of the TXD32 pin output data is inverted. 0: TXD32 output data is not inverted 1: TXD32 output data is inverted 2 SCINV2 0 R/W RXD32 Pin Input Data Inversion Switch This bit selects whether or not the logic level of the RXD32 pin input data is inverted. 0: RXD32 input data is not inverted 1: RXD32 input data is inverted 1, 0 W Reserved The write value should always be 0. Note: When the serial port control register is modified, the data being input or output up to that point is inverted immediately after the modification, and an invalid data change is input or output. When modifying the serial port control register, modification must be made in a state in which data changes are invalidated. Rev. 1.00 Dec. 13, 2007 Page 237 of 380 REJ09B0430-0100 Section 10 Serial Communication Interface 3 (SCI3) 10.4 Operation in Asynchronous Mode Figure 10.2 shows the general format for asynchronous serial communication. One frame consists of a start bit (low level), followed by data (in LSB-first order), a parity bit (high or low level), and finally stop bits (high level). In asynchronous mode, synchronization is performed at the falling edge of the start bit during reception. The data is sampled on the 8th pulse of a clock with a frequency 16 times the bit period, so that the transfer data is latched at the center of each bit. Inside the SCI3, the transmitter and receiver are independent units, enabling full duplex. Both the transmitter and the receiver also have a double-buffered structure, so data can be read or written during transmission or reception, enabling continuous data transfer. Table 10.7 shows the 16 data transfer formats that can be set in asynchronous mode. The format is selected by the settings in SMR as shown in table 10.8. LSB Serial Start data bit Transmit/receive data MSB Parity bit Stop bit 1 Mark state 1 bit 5, 7, or 8 bits 1 bit, or none 1 or 2 bits One unit of transfer data (character or frame) Figure 10.2 Data Format in Asynchronous Communication Rev. 1.00 Dec. 13, 2007 Page 238 of 380 REJ09B0430-0100 Section 10 Serial Communication Interface 3 (SCI3) 10.4.1 Clock Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK32 pin can be selected as the SCI3's serial clock source, according to the setting of the COM bit in SMR and the CKE0 and CKE1 bits in SCR3. For details on selection of the clock source, see table 10.9. When an external clock is input at the SCK32 pin, the clock frequency should be 16 times the bit rate used. When the SCI3 is operated on an internal clock, the clock can be output from the SCK32 pin. The frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is in the middle of the transmit data, as shown in figure 10.3. Clock Serial data 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1 1 character (frame) Figure 10.3 Relationship between Output Clock and Transfer Data Phase (Asynchronous Mode) (Example with 8-Bit Data, Parity, Two Stop Bits) Rev. 1.00 Dec. 13, 2007 Page 239 of 380 REJ09B0430-0100 Section 10 Serial Communication Interface 3 (SCI3) Table 10.7 Data Transfer Formats (Asynchronous Mode) SMR CHR 0 PE 0 MP 0 STOP 0 1 START Serial Data Transfer Format and Frame Length 2 3 4 5 6 7 8 9 10 STOP 11 12 8-bit data 0 0 0 1 START 8-bit data STOP STOP 0 0 1 0 Setting prohibited 0 0 1 1 Setting prohibited 0 1 0 0 START 8-bit data P STOP 0 1 0 1 START 8-bit data P STOP STOP 0 1 1 0 START 5-bit data STOP 0 1 1 1 START 5-bit data STOP STOP 1 0 0 0 START 7-bit data STOP 1 0 0 1 START 7-bit data STOP STOP 1 0 1 0 Setting prohibited 1 0 1 1 Setting prohibited 1 1 0 0 START 7-bit data P STOP 1 1 0 1 START 7-bit data P STOP STOP 1 1 1 0 START 5-bit data P STOP 1 [Legend] 1 1 1 START 5-bit data P STOP STOP START: Start bit STOP: Stop bit P: MPB Parity bit Multiprocessor bit Rev. 1.00 Dec. 13, 2007 Page 240 of 380 REJ09B0430-0100 Section 10 Serial Communication Interface 3 (SCI3) Table 10.8 SMR Settings and Corresponding Data Transfer Formats SMR Bit 7 COM 0 Bit 6 CHR 0 Bit 2 MP 0 Bit 5 PE 0 Bit 3 STOP 0 1 1 0 1 1 0 0 1 1 0 1 0 1 0 0 1 1 0 1 1 0 0 1 1 0 1 1 * 0 * * Asynchronous 5-bit data No mode Clock synchronous mode 8-bit data No Yes 1 bit 2 bits No No Asynchronous 5-bit data No mode Setting prohibited No 1 bit 2 bits Setting prohibited Yes 7-bit data No Mode Data Length Data Transfer Format Multiprocessor Bit Parity Bit No Stop Bit Length 1 bit 2 bits Yes 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits Asynchronous 8-bit data No mode [Legend] *: Don't care Rev. 1.00 Dec. 13, 2007 Page 241 of 380 REJ09B0430-0100 Section 10 Serial Communication Interface 3 (SCI3) Table 10.9 SMR and SCR3 Settings and Clock Source Selection SMR Bit 7 COM 0 Bit 1 CKE1 0 SCR3 Bit 0 CKE0 0 1 1 1 0 1 0 1 1 1 0 1 0 0 0 1 1 1 Mode Asynchronous mode Transmit/Receive Clock Clock Source Internal SCK32 Pin Function I/O port (SCK32 pin not used) Outputs clock with same frequency as bit rate External Clocked Internal synchronous mode External Inputs clock with frequency 16 times bit rate Outputs serial clock Inputs serial clock Reserved (Do not specify these combinations) Rev. 1.00 Dec. 13, 2007 Page 242 of 380 REJ09B0430-0100 Section 10 Serial Communication Interface 3 (SCI3) 10.4.2 SCI3 Initialization Follow the flowchart as shown in figure 10.4 to initialize the SCI3. When the TE bit is cleared to 0, the TDRE flag is set to 1. Note that clearing the RE bit to 0 does not initialize the contents of the RDRF, PER, FER, and OER flags, or the contents of RDR. When the external clock is used in asynchronous mode, the clock must be supplied even during initialization. When the external clock is used in clock synchronous mode, the clock must not be supplied during initialization. [1] Start initialization Set the clock selection in SCR3. Be sure to clear bits RIE, TIE, TEIE, and MPIE, and bits TE and RE, to 0. When the clock output is selected in asynchronous mode, clock is output immediately after CKE1 and CKE0 settings are made. When the clock output is selected at reception in clocked synchronous mode, clock is output immediately after CKE1, CKE0, and RE are set to 1. [2] [3] No 1-bit interval elapsed? Yes Set SPC32 bit in SPCR to 1 Set TE and RE bits in SCR3 to 1, and set RIE, TIE, TEIE, and MPIE bits. [4] [4] Set the data transfer format in SMR. Write a value corresponding to the bit rate to BRR. Not necessary if an external clock is used. Wait at least one bit interval, then set the TE bit or RE bit in SCR3 to 1. Setting bits TE and RE enables the TXD32 and RXD32 pins to be used. Also set the RIE, TIE, TEIE, and MPIE bits, depending on whether interrupts are required. In asynchronous mode, the bits are marked at transmission and idled at reception to wait for the start bit. Clear TE and RE bits in SCR3 to 0 [1] Set CKE1 and CKE0 bits in SCR3 Set data transfer format in SMR [2] Set value in BRR Wait [3] Figure 10.4 Sample SCI3 Initialization Flowchart Rev. 1.00 Dec. 13, 2007 Page 243 of 380 REJ09B0430-0100 Section 10 Serial Communication Interface 3 (SCI3) 10.4.3 Data Transmission Figure 10.5 shows an example of operation for transmission in asynchronous mode. In transmission, the SCI3 operates as described below. 1. 2. The SCI3 monitors the TDRE flag in SSR. If the flag is cleared to 0, the SCI3 recognizes that data has been written to TDR, and transfers the data from TDR to TSR. After transferring data from TDR to TSR, the SCI3 sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a TXI interrupt request is generated. Continuous transmission is possible because the TXI interrupt routine writes next transmit data to TDR before transmission of the current transmit data has been completed. The SCI3 checks the TDRE flag at the timing for sending the stop bit. If the TDRE flag is 0, the data is transferred from TDR to TSR, the stop bit is sent, and then serial transmission of the next frame is started. If the TDRE flag is 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the "mark state" is entered, in which 1 is output. If the TEIE bit in SCR3 is set to 1 at this time, a TEI interrupt request is generated. Figure 10.6 shows a sample flowchart for transmission in asynchronous mode. Start bit Serial data 1 0 D0 D1 1 frame Transmit data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 Transmit data D1 1 frame D7 Parity Stop bit bit 0/1 1 Mark state 1 3. 4. 5. 6. TDRE TEND TXI interrupt LSI operation request generated User processing TDRE flag cleared to 0 Data written to TDR TXI interrupt request generated TEI interrupt request generated Figure 10.5 Example SCI3 Operation in Transmission in Asynchronous Mode (8-Bit Data, Parity, One Stop Bit) Rev. 1.00 Dec. 13, 2007 Page 244 of 380 REJ09B0430-0100 Section 10 Serial Communication Interface 3 (SCI3) Start transmission Set SPC32 bit in SPCR to 1 [1] Read TDRE flag in SSR No TDRE = 1 Yes Write transmit data to TDR [2] Yes All data transmitted? No [1] Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. When data is written to TDR, the TDRE flag is automaticaly cleared to 0. (After the TE bit is set to 1, one frame of 1 is output, then transmission is possible.) [2] To continue serial transmission, read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR. When data is written to TDR, the TDRE flag is automaticaly cleared to 0. [3] To output a break in serial transmission, after setting PCR to 1 and PDR to 0, clear the TE bit in SCR3 to 0. Read TEND flag in SSR No TEND = 1 Yes No Break output? Yes Clear PDR to 0 and set PCR to 1 [3] Clear TE bit in SCR3 to 0 Figure 10.6 Sample Serial Transmission Flowchart (Asynchronous Mode) Rev. 1.00 Dec. 13, 2007 Page 245 of 380 REJ09B0430-0100 Section 10 Serial Communication Interface 3 (SCI3) 10.4.4 Serial Data Reception Figure 10.7 shows an example of operation for reception in asynchronous mode. In serial reception, the SCI operates as described below. 1. The SCI3 monitors the communication line. If a start bit is detected, the SCI3 performs internal synchronization, receives data in RSR, and checks the parity bit and stop bit. * Parity check The SCI3 checks that the number of 1 bits in the receive data conforms to the parity (odd or even) set in bit PM in the serial mode register (SMR). * Stop bit check The SCI3 checks that the stop bit is 1. If two stop bits are used, only the first is checked. * Status check The SCI3 checks that bit RDRF is set to 0, indicating that the receive data can be transferred from RSR to RDR. 2. If an overrun error occurs (when reception of the next data is completed while the RDRF flag is still set to 1), the OER bit in SSR is set to 1. If the RIE bit in SCR3 is set to 1 at this time, an ERI interrupt request is generated. Receive data is not transferred to RDR. If a parity error is detected, the PER bit in SSR is set to 1 and receive data is transferred to RDR. If the RIE bit in SCR3 is set to 1 at this time, an ERI interrupt request is generated. If a framing error is detected (when the stop bit is 0), the FER bit in SSR is set to 1 and receive data is transferred to RDR. If the RIE bit in SCR3 is set to 1 at this time, an ERI interrupt request is generated. If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is transferred to RDR. If the RIE bit in SCR3 is set to 1 at this time, an RXI interrupt request is generated. Continuous reception is possible because the RXI interrupt routine reads the receive data transferred to RDR before reception of the next receive data has been completed. 3. 4. 5. Rev. 1.00 Dec. 13, 2007 Page 246 of 380 REJ09B0430-0100 Section 10 Serial Communication Interface 3 (SCI3) Start bit Serial data 1 0 D0 D1 Receive data D7 1 frame Parity Stop Start bit bit bit 0/1 1 0 D0 Receive data D1 1 frame D7 Parity Stop bit bit 0/1 0 Mark state (idle state) 1 RDRF FER LSI operation User processing RXI request RDRF cleared to 0 RDR data read 0 stop bit detected ERI request in response to framing error Framing error processing Figure 10.7 Example SCI3 Operation in Reception in Asynchronous Mode (8-Bit Data, Parity, One Stop Bit) Table 10.10 shows the states of the SSR status flags and receive data handling when a receive error is detected. If a receive error is detected, the RDRF flag retains its state before receiving data. Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the OER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 10.8 shows a sample flowchart for serial data reception. Table 10.10 SSR Status Flags and Receive Data Handling SSR Status Flag RDRF* 1 0 0 1 1 0 1 Note: * OER 1 0 0 1 1 0 1 FER 0 1 0 1 0 1 1 PER 0 0 1 0 1 1 1 Receive Data Lost Transferred to RDR Transferred to RDR Lost Lost Transferred to RDR Lost Receive Error Type Overrun error Framing error Parity error Overrun error + framing error Overrun error + parity error Framing error + parity error Overrun error + framing error + parity error The RDRF flag retains the state it had before data reception. However, note that if RDR is read after an overrun error has occurred in a frame because reading of the receive data in the previous frame was delayed, the RDRF flag will be cleared to 0. Rev. 1.00 Dec. 13, 2007 Page 247 of 380 REJ09B0430-0100 Section 10 Serial Communication Interface 3 (SCI3) Start reception Read OER, PER, and FER flags in SSR [1] Yes OER+PER+FER = 1 [4] No Error processing (Continued on next page) Read RDRF flag in SSR No RDRF = 1 Yes [2] Read receive data in RDR [1] Read the OER, PER, and FER flags in SSR to identify the error. If a receive error occurs, performs the appropriate error processing. [2] Read SSR and check that RDRF = 1, then read the receive data in RDR. The RDRF flag is cleared automatically. [3] To continue serial reception, before the stop bit for the current frame is received, read the RDRF flag and read RDR. The RDRF flag is cleared automatically. [4] If a receive error occurs, read the OER, PER, and FER flags in SSR to identify the error. After performing the appropriate error processing, ensure that the OER, PER, and FER flags are all cleared to 0. Reception cannot be resumed if any of these flags are set to 1. In the case of a framing error, a break can be detected by reading the value of the input port corresponding to the RXD32 pin. Yes All data received? (A) No Clear RE bit in SCR3 to 0 Figure 10.8 Sample Serial Data Reception Flowchart (Asynchronous Mode) (1) Rev. 1.00 Dec. 13, 2007 Page 248 of 380 REJ09B0430-0100 Section 10 Serial Communication Interface 3 (SCI3) [4] Error processing No OER = 1 Yes Overrun error processing No FER = 1 Yes Yes Break? No Framing error processing No PER = 1 Yes Parity error processing (A) Clear OER, PER, and FER flags in SSR to 0 Figure 10.8 Sample Serial Data Reception Flowchart (Asynchronous Mode) (2) Rev. 1.00 Dec. 13, 2007 Page 249 of 380 REJ09B0430-0100 Section 10 Serial Communication Interface 3 (SCI3) 10.5 Operation in Clocked Synchronous Mode Figure 10.9 shows the general format for clock synchronous communication. In clock synchronous mode, data is transmitted or received synchronous with clock pulses. A single character in the transmit data consists of the 8-bit data starting from the LSB. In clock synchronous serial communication, data on the transmission line is output from one falling edge of the serial clock to the next. In clock synchronous mode, the SCI3 receives data in synchronous with the rising edge of the serial clock. After 8-bit data is output, the transmission line holds the MSB state. In clock synchronous mode, no parity or multiprocessor bit is added. Inside the SCI3, the transmitter and receiver are independent units, enabling full-duplex communication through the use of a common clock. Both the transmitter and the receiver also have a double-buffered structure, so data can be read or written during transmission or reception, enabling continuous data transfer. 8-bit * Synchronization clock LSB Serial data Don't care Note: * High except in continuous transfer Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB Bit 7 Don't care One unit of transfer data (character or frame) * Figure 10.9 Data Format in Clocked Synchronous Communication 10.5.1 Clock Either an internal clock generated by the on-chip baud rate generator or an external synchronization clock input at the SCK32 pin can be selected, according to the setting of the COM bit in SMR and CKE0 and CKE1 bits in SCR3. When the SCI3 is operated on an internal clock, the serial clock is output from the SCK32 pin. Eight serial clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high. 10.5.2 SCI3 Initialization Before transmitting and receiving data, the SCI3 should be initialized as described in a sample flowchart in figure 10.4. Rev. 1.00 Dec. 13, 2007 Page 250 of 380 REJ09B0430-0100 Section 10 Serial Communication Interface 3 (SCI3) 10.5.3 Serial Data Transmission Figure 10.10 shows an example of SCI3 operation for transmission in clock synchronous mode. In serial transmission, the SCI3 operates as described below. 1. 2. 3. The SCI3 monitors the TDRE flag in SSR, and if the flag is 0, the SCI recognizes that data has been written to TDR, and transfers the data from TDR to TSR. The SCI3 sets the TDRE flag to 1 and starts transmission. If the TIE bit in SCR3 is set to 1 at this time, a transmit data empty interrupt (TXI) is generated. 8-bit data is sent from the TXD32 pin synchronized with the output clock when output clock mode has been specified, and synchronized with the input clock when use of an external clock has been specified. Serial data is transmitted sequentially from the LSB (bit 0), from the TXD32 pin. The SCI checks the TDRE flag at the timing for sending the MSB (bit 7). If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission of the next frame is started. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, and the TDRE flag maintains the output state of the last bit. If the TEIE bit in SCR3 is set to 1 at this time, a TEI interrupt request is generated. The SCK32 pin is fixed high. 4. 5. 6. 7. Figure 10.11 shows a sample flowchart for serial data transmission. Even if the TDRE flag is cleared to 0, transmission will not start while a receive error flag (OER, FER, or PER) is set to 1. Make sure that the receive error flags are cleared to 0 before starting transmission. Rev. 1.00 Dec. 13, 2007 Page 251 of 380 REJ09B0430-0100 Section 10 Serial Communication Interface 3 (SCI3) Serial clock Serial data Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 1 frame TDRE TEND LSI TXI interrupt operation request generated User processing TDRE flag cleared to 0 Data written to TDR 1 frame TXI interrupt request generated TEI interrupt request generated Figure 10.10 Example of SCI3 Operation in Transmission in Clocked Synchronous Mode Rev. 1.00 Dec. 13, 2007 Page 252 of 380 REJ09B0430-0100 Section 10 Serial Communication Interface 3 (SCI3) Start transmission Set SPC32 bit in SPCR to 1 [1] [1] Read TDRE flag in SSR No TDRE = 1 [2] Yes Write transmit data to TDR Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0. When clock output is selected and data is written to TDR, clocks are output to start the data transmission. To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0. [2] All data transmitted? No Yes Read TEND flag in SSR No TEND = 1 Yes Clear TE bit in SCR3 to 0 Figure 10.11 Sample Serial Transmission Flowchart (Clocked Synchronous Mode) Rev. 1.00 Dec. 13, 2007 Page 253 of 380 REJ09B0430-0100 Section 10 Serial Communication Interface 3 (SCI3) 10.5.4 Serial Data Reception Figure 10.12 shows an example of SCI3 operation for reception in clock synchronous mode. In serial reception, the SCI3 operates as described below. 1. 2. 3. The SCI3 performs internal initialization synchronous with a synchronous clock input or output, starts receiving data. The SCI3 stores the received data in RSR. If an overrun error occurs (when reception of the next data is completed while the RDRF flag in SSR is still set to 1), the OER bit in SSR is set to 1. If the RIE bit in SCR3 is set to 1 at this time, an ERI interrupt request is generated, receive data is not transferred to RDR, and the RDRF flag remains to be set to 1. If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is transferred to RDR. If the RIE bit in SCR3 is set to 1 at this time, an RXI interrupt request is generated. 4. Serial clock Serial data Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 1 frame RDRF OER LSI operation User processing RXI interrupt request generated RDRF flag cleared to 0 RDR data read 1 frame RXI interrupt request generated ERI interrupt request generated by overrun error Overrun error processing RDR data has not been read (RDRF = 1) Figure 10.12 Example of SCI3 Reception Operation in Clocked Synchronous Mode Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the OER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 10.13 shows a sample flowchart for serial data reception. Rev. 1.00 Dec. 13, 2007 Page 254 of 380 REJ09B0430-0100 Section 10 Serial Communication Interface 3 (SCI3) Start reception [1] Read OER flag in SSR [1] [2] Yes OER = 1 [4] No Error processing (Continued below) Read RDRF flag in SSR [2] [4] RDRF = 1 Yes [3] Read the OER flag in SSR to determine if there is an error. If an overrun error has occurred, execute overrun error processing. Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR. When data is read from RDR, the RDRF flag is automatically cleared to 0. To continue serial reception, before the MSB (bit 7) of the current frame is received, reading the RDRF flag and reading RDR should be finished. When data is read from RDR, the RDRF flag is automatically cleared to 0. If an overrun error occurs, read the OER flag in SSR, and after performing the appropriate error processing, clear the OER flag to 0. Reception cannot be resumed if the OER flag is set to 1. No Read receive data in RDR Yes All data received? No Clear RE bit in SCR3 to 0 [4] Error processing Overrun error processing Clear OER flag in SSR to 0 Figure 10.13 Sample Serial Reception Flowchart (Clocked Synchronous Mode) Rev. 1.00 Dec. 13, 2007 Page 255 of 380 REJ09B0430-0100 Section 10 Serial Communication Interface 3 (SCI3) 10.5.5 Simultaneous Serial Data Transmission and Reception Figure 10.14 shows a sample flowchart for simultaneous serial transmit and receive operations. The following procedure should be used for simultaneous serial data transmit and receive operations. To switch from transmit mode to simultaneous transmit and receive mode, after checking that the SCI3 has finished transmission and the TDRE and TEND flags are set to 1, clear TE to 0. Then simultaneously set TE and RE to 1 with a single instruction. To switch from receive mode to simultaneous transmit and receive mode, after checking that the SCI3 has finished reception, clear RE to 0. Then after checking that the RDRF and receive error flags (OER, FER, and PER) are cleared to 0, simultaneously set TE and RE to 1 with a single instruction. Rev. 1.00 Dec. 13, 2007 Page 256 of 380 REJ09B0430-0100 Section 10 Serial Communication Interface 3 (SCI3) Start transmission/reception Set SPC32 bit in SPCR to 1 Read TDRE flag in SSR No TDRE = 1 Yes Write transmit data to TDR [1] Read OER flag in SSR Yes [4] Error processing OER = 1 No Read RDRF flag in SSR No RDRF = 1 Yes Read receive data in RDR [2] Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0. [2] Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR. When data is read from RDR, the RDRF flag is automatically cleared to 0. [3] To continue serial transmission/ reception, before the MSB (bit 7) of the current frame is received, finish reading the RDRF flag, reading RDR. Also, before the MSB (bit 7) of the current frame is transmitted, read 1 from the TDRE flag to confirm that writing is possible. Then write data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0. When data is read from RDR, the RDRF flag is automatically cleared to 0. [4] If an overrun error occurs, read the OER flag in SSR, and after performing the appropriate error processing, clear the OER flag to 0. Transmission/reception cannot be resumed if the OER flag is set to 1. For overrun error processing, see figure 10.13. [1] Yes All data received? No [3] Clear TE and RE bits in SCR to 0 Figure 10.14 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations (Clocked Synchronous Mode) Rev. 1.00 Dec. 13, 2007 Page 257 of 380 REJ09B0430-0100 Section 10 Serial Communication Interface 3 (SCI3) 10.6 Interrupts The SCI3 creates the following six interrupt requests: transmission end, transmit data empty, receive data full, and receive errors (overrun error, framing error, and parity error). Table 10.11 shows the interrupt sources. Table 10.11 SCI3 Interrupt Requests Interrupt Requests Receive Data Full Transmit Data Empty Transmission End Receive Error Abbreviation RXI TXI TEI ERI Interrupt Sources Setting RDRF in SSR Setting TDRE in SSR Setting TEND in SSR Setting OER, FER, or PER in SSR Enable Bit RIE TIE TEIE RIE Each interrupt request can be enabled or disabled by means of bits TIE, RIE and TEIE in SCR3. When bit TDRE is set to 1 in SSR, a TXI interrupt is requested. When bit TEND is set to 1 in SSR, a TEI interrupt is requested. These two interrupts are generated during transmission. The initial value of the TDRE flag in SSR is 1. Thus, when the TIE bit in SCR3 is set to 1 before transferring the transmit data to TDR, a TXI interrupt request is generated even if the transmit data is not ready. The initial value of the TEND flag in SSR is 1. Thus, when the TEIE bit in SCR3 is set to 1 before transferring the transmit data to TDR, a TEI interrupt request is generated even if the transmit data has not been sent. It is possible to make use of the most of these interrupt requests efficiently by transferring the transmit data to TDR in the interrupt routine. To prevent the generation of these interrupt requests (TXI and TEI), set the enable bits (TIE and TEIE) that correspond to these interrupt requests to 1, after transferring the transmit data to TDR. When bit RDRF is set to 1 in SSR, an RXI interrupt is requested, and if any of bits OER, PER, and FER is set to 1, an ERI interrupt is requested. These two interrupt requests are generated during reception. For further details, see section 3, Exception Handling. The SCI3 can carry out continuous reception using RXI and continuous transmission using TXI. These interrupts are shown in table 10.12. Rev. 1.00 Dec. 13, 2007 Page 258 of 380 REJ09B0430-0100 Section 10 Serial Communication Interface 3 (SCI3) Table 10.12 Transmit/Receive Interrupts Flag and Enable Bit Interrupt Request Conditions RDRF RIE When serial reception is performed normally and receive data is transferred from RSR to RDR, bit RDRF is set to 1, and if bit RIE is set to 1 at this time, RXI is enabled and an interrupt is requested. (See figure 10.15(a).) When TSR is found to be empty (on completion of the previous transmission) and the transmit data placed in TDR is transferred to TSR, bit TDRE is set to 1. If bit TIE is set to 1 at this time, TXI is enabled and an interrupt is requested. (See figure 10.15(b).) When the last bit of the character in TSR is transmitted, if bit TDRE is set to 1, bit TEND is set to 1. If bit TEIE is set to 1 at this time, TEI is enabled and an interrupt is requested. (See figure 10.15(c).) Interrupt RXI Notes The RXI interrupt routine reads the receive data transferred to RDR and clears bit RDRF to 0. Continuous reception can be performed by repeating the above operations until reception of the next RSR data is completed. The TXI interrupt routine writes the next transmit data to TDR and clears bit TDRE to 0. Continuous transmission can be performed by repeating the above operations until the data transferred to TSR has been transmitted. TEI indicates that the next transmit data has not been written to TDR when the last bit of the transmit character in TSR is transmitted. TXI TDRE TIE TEI TEND TEIE RDR RDR RSR (reception in progress) RXD32 pin RXD32 pin RSR (reception completed, transfer) RDRF = 0 RDRF (RXI request when RIE = 1) Figure 10.15(a) RDRF Setting and RXI Interrupt Rev. 1.00 Dec. 13, 2007 Page 259 of 380 REJ09B0430-0100 1 Section 10 Serial Communication Interface 3 (SCI3) TDR (next transmit data) TDR TSR (transmission in progress) TXD32 pin TXD32 pin TSR (transmission completed, transfer) TDRE = 0 TDRE (TXI request when TIE = 1) Figure 10.15(b) TDRE Setting and TXI Interrupt TDR TDR TSR (transmission in progress) TXD32 pin TXD32 pin TSR (transmission completed) TEND = 0 TEND (TEI request when TEIE = 1) Figure 10.15(c) TEND Setting and TEI Interrupt Rev. 1.00 Dec. 13, 2007 Page 260 of 380 REJ09B0430-0100 1 1 Section 10 Serial Communication Interface 3 (SCI3) 10.7 10.7.1 Usage Notes Break Detection and Processing When framing error detection is performed, a break can be detected by reading the RXD32 pin value directly. In a break, the input from the RXD32 pin becomes all 0, setting the FER flag, and possibly the PER flag. Note that as the SCI3 continues the receive operation after receiving a break, even if the FER flag is cleared to 0, it will be set to 1 again. 10.7.2 Mark State and Break Sending When TE is 0, the TXD32 pin is used as an I/O port whose direction (input or output) and level are determined by PCR and PDR. This can be used to set the TXD32 pin to mark state (high level) or send a break during serial data transmission. To maintain the communication line at mark state until TE is set to 1, set both PCR and PDR to 1. As TE is cleared to 0 at this point, the TXD32 pin becomes an I/O port, and 1 is output from the TXD32 pin. To send a break during serial transmission, first set PCR to 1 and PDR to 0, and then clear TE to 0. When TE is cleared to 0, the transmitter is initialized regardless of the current transmission state, the TXD32 pin becomes an I/O port, and 0 is output from the TXD32 pin. 10.7.3 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only) Transmission cannot be started when a receive error flag (OER, PER, or FER) is set to 1, even if the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting transmission. Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared to 0. 10.7.4 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode In asynchronous mode, the SCI3 operates on a basic clock with a frequency of 16 times the transfer rate. In reception, the SCI3 samples the falling edge of the start bit using the basic clock, and performs internal synchronization. Receive data is latched internally at the rising edge of the 8th pulse of the basic clock as shown in figure 10.16. Rev. 1.00 Dec. 13, 2007 Page 261 of 380 REJ09B0430-0100 Section 10 Serial Communication Interface 3 (SCI3) Thus, the reception margin in asynchronous mode is given by formula (1) below. 1 D - 0.5 M = (0.5 - )- - (L - 0.5) F * 100(%) 2N N ... Formula (1) Where N D L F : Ratio of bit rate to clock (N = 16) : Clock duty (D = 0.5 to 1.0) : Frame length (L = 9 to 12) : Absolute value of clock rate deviation Assuming values of F (absolute value of clock rate deviation) = 0 and D (clock duty) = 0.5 in formula (1), the reception margin can be given by the formula. M = {0.5 - 1/(2 16)} x 100 [%] = 46.875% However, this is only the computed value, and a margin of 20% to 30% should be allowed for in system design. 16 clocks 8 clocks 0 Internal basic clock Receive data (RXD32) Synchronization sampling timing Data sampling timing 7 15 0 7 15 0 Start bit D0 D1 Figure 10.16 Receive Data Sampling Timing in Asynchronous Mode Rev. 1.00 Dec. 13, 2007 Page 262 of 380 REJ09B0430-0100 Section 10 Serial Communication Interface 3 (SCI3) 10.7.5 Note on Switching SCK32 Function If pin SCK32 is used as a clock output pin by the SCI3 in clock synchronous mode and is then switched to a general input/output pin (a pin with a different function), the pin outputs a low level signal for half a system clock () cycle immediately after it is switched. This can be prevented by either of the following methods according to the situation. a. When an SCK32 function is switched from clock output to non clock-output When stopping data transfer, issue one instruction to clear bits TE and RE to 0 and to set bits CKE1 and CKE0 in SCR3 to 1 and 0, respectively. In this case, bit COM in SMR should be left 1. The above prevents SCK32 from being used as a general input/output pin. To avoid an intermediate level of voltage from being applied to SCK32, the line connected to SCK32 should be pulled up to the VCC level via a resistor, or supplied with output from an external device. b. When an SCK32 function is switched from clock output to general input/output When stopping data transfer, (i) Issue one instruction to clear bits TE and RE to 0 and to set bits CKE1 and CKE0 in SCR3 to 1 and 0, respectively. (ii) Clear bit COM in SMR to 0 (iii) Clear bits CKE1 and CKE0 in SCR3 to 0 Note that special care is also needed here to avoid an intermediate level of voltage from being applied to SCK32. Relation between Writing to TDR and Bit TDRE 10.7.6 Bit TDRE in the serial status register (SSR) is a status flag that indicates that data for serial transmission has not been prepared in TDR. When data is written to TDR, bit TDRE is cleared to 0 automatically. When the SCI3 transfers data from TDR to TSR, bit TDRE is set to 1. Data can be written to TDR irrespective of the state of bit TDRE, but if new data is written to TDR while bit TDRE is cleared to 0, the data previously stored in TDR will be lost if it has not yet been transferred to TSR. Accordingly, to ensure that serial transmission is performed dependably, you should first check that bit TDRE is set to 1, then write the transmit data to TDR only once (not two or more times). Rev. 1.00 Dec. 13, 2007 Page 263 of 380 REJ09B0430-0100 Section 10 Serial Communication Interface 3 (SCI3) 10.7.7 Relation between RDR Reading and bit RDRF In a receive operation, the SCI3 continually checks the RDRF flag. If bit RDRF is cleared to 0 when reception of one frame ends, normal data reception is completed. If bit RDRF is set to 1, this indicates that an overrun error has occurred. When the contents of RDR are read, bit RDRF is cleared to 0 automatically. Therefore, if RDR is read more than once, the second and subsequent read operations will be performed while bit RDRF is cleared to 0. Note that, when an RDR read is performed while bit RDRF is cleared to 0, if the read operation coincides with completion of reception of a frame, the next frame of data may be read. This is shown in figure 10.17. Frame 1 Frame 2 Frame 3 Communication line Data 1 Data 2 Data 3 RDRF RDR Data 1 (A) RDR read Data 2 (B) RDR read Data 1 is read at point (A) Data 2 is read at point (B) Figure 10.17 Relation between RDR Read Timing and Data In this case, only a single RDR read operation (not two or more) should be performed after first checking that bit RDRF is set to 1. If two or more reads are performed, the data read the first time should be transferred to RAM, etc., and the RAM contents used. Also, ensure that there is sufficient margin in an RDR read operation before reception of the next frame is completed. To be precise in terms of timing, the RDR read should be completed before bit 7 is transferred in clock synchronous mode, or before the STOP bit is transferred in asynchronous mode. 10.7.8 Transmit and Receive Operations when Making State Transition Make sure that transmit and receive operations have completely finished before carrying out state transition processing. Rev. 1.00 Dec. 13, 2007 Page 264 of 380 REJ09B0430-0100 Section 10 Serial Communication Interface 3 (SCI3) 10.7.9 Setting in Subactive or Subsleep Mode In subactive or subsleep mode, the SCI3 can operate only when the CPU clock is W/2. The SA1 bit in SYSCR2 should be set to 1. Rev. 1.00 Dec. 13, 2007 Page 265 of 380 REJ09B0430-0100 Section 10 Serial Communication Interface 3 (SCI3) Rev. 1.00 Dec. 13, 2007 Page 266 of 380 REJ09B0430-0100 Section 11 10-Bit PWM Section 11 10-Bit PWM This LSI has a two-channel 10-bit PWM. The PWM with a low-path filter connected can be used as a D/A converter. Figure 11.1 shows a block diagram of the 10-bit PWM. 11.1 Features * Choice of four conversion periods A conversion period of 4096/ with a minimum modulation width of 4/, a conversion period of 2048/ with a minimum modulation width of 2/, a conversion period of 1024/ with a minimum modulation width of 1/, or a conversion period of 512/ with a minimum modulation width of 1/2 can be selected. * Pulse division method for less ripple * Use of module standby mode enables this module to be placed in standby mode independently when not used. (For details, refer to section 5.4, Module Standby Function.) PWCR PWDRL PWDRU /8 /4 /2 [Legend] PWCR: PWDRL: PWDRU: PWM: PWM waveform generator Internal data bus PWM PWM control register PWM data register L PWM data register U PWM output pin Figure 11.1 Block Diagram of 10-Bit PWM Rev. 1.00 Dec. 13, 2007 Page 267 of 380 REJ09B0430-0100 Section 11 10-Bit PWM 11.2 Input/Output Pins Table 11.1 shows the 10-bit PWM pin configuration. Table 11.1 Pin Configuration Name 10-bit PWM square-wave output 1 10-bit PWM square-wave output 2 Abbreviation PWM1 I/O Output Function Channel 1: 10-bit PWM waveform output pin/event counter PWM output pin Channel 2: 10-bit PWM waveform output pin/event counter PWM output pin PWM2 Output Rev. 1.00 Dec. 13, 2007 Page 268 of 380 REJ09B0430-0100 Section 11 10-Bit PWM 11.3 Register Descriptions The 10-bit PWM has the following registers. * PWM control register (PWCR) * PWM data register U (PWDRU) * PWM data register L (PWDRL) 11.3.1 PWM Control Register (PWCR) PWCR selects the conversion period. Bit 7 6 5 4 3 2 1 0 Bit Name PWCR1 PWCR0 Initial Value 1 1 1 1 1 1 0 0 R/W W W Clock Select 1, 0 00: The input clock is (t = 1/) The conversion period is 512/, with a minimum modulation width of 1/2 01: The input clock is /2 (t = 2/) The conversion period is 1024/, with a minimum modulation width of 1/ 10: The input clock is /4 (t = 4/) The conversion period is 2048/, with a minimum modulation width of 2/ 11: The input clock is /8 (t = 8/) The conversion period is 4096/, with a minimum modulation width of 4/ [Legend] t: Period of PWM clock input Description Reserved These bits are always read as 1, and cannot be modified. Rev. 1.00 Dec. 13, 2007 Page 269 of 380 REJ09B0430-0100 Section 11 10-Bit PWM 11.3.2 PWM Data Registers U and L (PWDRU, PWDRL) PWDRU and PWDRL indicate high level width in one PWM waveform cycle. PWDRU and PWDRL are 10-bit write-only registers, with the upper 2 bits assigned to PWDRU and the lower 8 bits to PWDRL. When read, all bits are always read as 1. Both PWDRU and PWDRL are accessible only in bytes. Note that the operation is not guaranteed if word access is performed. When 10-bit data is written in PWDRU and PWDRL, the contents are latched in the PWM waveform generator and the PWM waveform generation data is updated. When writing the 10-bit data, the order is as follows: PWDRL to PWDRU. PWDRU and PWDRL are initialized to H'FC00. Rev. 1.00 Dec. 13, 2007 Page 270 of 380 REJ09B0430-0100 Section 11 10-Bit PWM 11.4 11.4.1 Operation Operation When using the 10-bit PWM, set the registers in this sequence: 1. Set the PWM2 and/or PWM1 bits in port mode register 9 (PMR9) to 1 to set the P91/PWM2 pin or P90/PWM1 pin, or both, to function as PWM output pins. 2. Set the PWCR0 and PWCR1 bits in PWCR to select one conversion period of either. 3. Set the output waveform data in PWDRU and PWDRL. Be sure to write byte data first to PWDRL and then to PWDRU. When the data is written in PWDRU, the contents of these registers are latched in the PWM waveform generator, and the PWM waveform generation data is updated in synchronization with internal signals. One conversion period consists of four pulses, as shown in figure 11.2. The total high-level width during this period (TH) corresponds to the data in PWDRU and PWDRL. This relation can be expressed as follows: TH = (data value in PWDRU and PWDRL + 4) x t/2 where t is the period of PWM clock input: 1/ (PWCR1 = 0, PWCR0 = 0), 2/ (PWCR1 = 0, PWCR0 = 1), 4/ (PWCR1 = 1, PWCR0 = 0), or 8/ (PWCR1 = 1, PWCR0 = 1). If the data value in PWDRU and PWDRL is from H'FFFC to H'FFFF, the PWM output stays high. When the data value is H'FC3C, TH is calculated as follows: TH = 64 x t/2 = 32 x t tf1 One conversion period tf2 tf3 tf4 tH1 tH2 tH3 tH4 TH = tH1 + tH2 + tH3 + tH4 tf1 = tf2 = tf3 = tf4 Figure 11.2 Waveform Output by 10-Bit PWM Rev. 1.00 Dec. 13, 2007 Page 271 of 380 REJ09B0430-0100 Section 11 10-Bit PWM 11.4.2 PWM Operating States Table 11.2 shows the PWM operating states. Table 11.2 PWM Operating States Operating Mode PWCR PWDRU PWDRL Reset Reset Reset Reset Active Functions Functions Functions Sleep Functions Functions Functions Watch Retained Retained Retained Sub-active Sub-sleep Retained Retained Retained Retained Retained Retained Standby Retained Retained Retained Module Standby Retained Retained Retained Rev. 1.00 Dec. 13, 2007 Page 272 of 380 REJ09B0430-0100 Section 12 A/D Converter Section 12 A/D Converter This LSI includes a successive approximation type 10-bit A/D converter that allows up to four analog input channels to be selected. The block diagram of the A/D converter is shown in figure 12.1. 12.1 * * * * * Features 10-bit resolution Four input channels Conversion time: at least 12.4 s per channel ( = 5 MHz operation) Sample and hold function Conversion start method Software * Interrupt request An A/D conversion end interrupt request (ADI) can be generated * Use of module standby mode enables this module to be placed in standby mode independently when not used. (For details, refer to section 5.4, Module Standby Function.) Rev. 1.00 Dec. 13, 2007 Page 273 of 380 REJ09B0430-0100 Section 12 A/D Converter AMR ADSR AN0 AN1 AN2 AN3 AVCC Multiplexer + Comparator AVCC Reference voltage AVSS Control logic AVSS ADRRH ADRRL Internal data bus [Legend] AMR: ADSR: IRRAD: A/D mode register A/D start register A/D conversion end interrupt request flag IRRAD ADRRH, L: A/D result registers H and L Figure 12.1 Block Diagram of A/D Converter Rev. 1.00 Dec. 13, 2007 Page 274 of 380 REJ09B0430-0100 Section 12 A/D Converter 12.2 Input/Output Pins Table 12.1 shows the input pins used by the A/D converter. Table 12.1 Pin Configuration Pin Name Analog power supply pin Analog ground pin Analog input pin 0 Analog input pin 1 Analog input pin 2 Analog input pin 3 Abbreviation AVcc AVss AN0 AN1 AN2 AN3 I/O Input Input Input Input Input Input Function Power supply and reference voltage of analog part Ground and reference voltage of analog part Analog input pins 12.3 Register Descriptions The A/D converter has the following registers. * A/D result registers H and L (ADRRH and ADRRL) * A/D mode register (AMR) * A/D start register (ADSR) 12.3.1 A/D Result Registers H and L (ADRRH and ADRRL) ADRRH and ADRRL are 16-bit read-only registers that store the results of A/D conversion. The upper 8 bits of the data are stored in ADRRH, and the lower 2 bits in ADRRL. ADRRH and ADRRL can be read by the CPU at any time, but the ADRRH and ADRRL values during A/D conversion are undefined. After A/D conversion is completed, the conversion result is stored as 10-bit data, and this data is retained until the next conversion operation starts. The initial values of ADRRH and ADRRL are undefined. Rev. 1.00 Dec. 13, 2007 Page 275 of 380 REJ09B0430-0100 Section 12 A/D Converter 12.3.2 A/D Mode Register (AMR) AMR sets the A/D conversion time and analog input pins. Bit 7 Bit Name CKS Initial Value 0 R/W R/W Description Clock Select Sets the A/D conversion time. 0: Conversion time = 62 states 1: Conversion time = 31 states 6 5 4 3 2 1 0 CH3 CH2 CH1 CH0 0 1 1 0 0 0 0 R/W R/W R/W R/W R/W Reserved Only 0 can be written to this bit. Reserved These bits are always read as 1 and cannot be modified. Channel Select 3 to 0 Selects the analog input channel. 00XX: No channel selected 0100: AN0 0101: AN1 0110: AN2 0111: AN3 1XXX: Using prohibited The channel selection should be made while the ADSF bit is cleared to 0. [Legend] X: Don't care. Rev. 1.00 Dec. 13, 2007 Page 276 of 380 REJ09B0430-0100 Section 12 A/D Converter 12.3.3 A/D Start Register (ADSR) ADSR starts and stops the A/D conversion. Bit 7 Bit Name ADSF Initial Value 0 R/W R/W Description When this bit is set to 1, A/D conversion is started. When conversion is completed, the converted data is set in ADRRH and ADRRL and at the same time this bit is cleared to 0. If this bit is written to 0, A/D conversion can be forcibly terminated. Reserved These bits are always read as 1 and cannot be modified. 6 to 0 All 1 12.4 Operation The A/D converter operates by successive approximation with 10-bit resolution. When changing the conversion time or analog input channel, in order to prevent incorrect operation, first clear the bit ADSF to 0 in ADSR. 12.4.1 1. 2. 3. 4. A/D Conversion A/D conversion is started from the selected channel when the ADSF bit in ADSR is set to 1, according to software. When A/D conversion is completed, the result is transferred to the A/D result register. On completion of conversion, the IRRAD flag in IRR2 is set to 1. If the IENAD bit in IENR2 is set to 1 at this time, an A/D conversion end interrupt request is generated. The ADSF bit remains set to 1 during A/D conversion. When A/D conversion ends, the ADSF bit is automatically cleared to 0 and the A/D converter enters the wait state. Rev. 1.00 Dec. 13, 2007 Page 277 of 380 REJ09B0430-0100 Section 12 A/D Converter 12.4.2 Operating States of A/D Converter Table 12.2 shows the operating states of the A/D converter. Table 12.2 Operating States of A/D Converter Operating Mode AMR ADSR ADRRH ADRRL Reset Reset Reset Retained* Retained* Active Functions Functions Functions Functions Sleep Functions Functions Functions Functions Watch Retained Reset Retained Retained Sub-active Sub-sleep Standby Retained Reset Retained Retained Retained Reset Retained Retained Retained Reset Retained Retained Module Standby Retained Reset Retained Retained Note: * Undefined in a power-on reset. 12.5 Example of Use An example of how the A/D converter can be used is given below, using channel 1 (pin AN1) as the analog input channel. Figure 12.2 shows the operation timing. 1. Bits CH3 to CH0 in the A/D mode register (AMR) are set to 0101, making pin AN1 the analog input channel. A/D interrupts are enabled by setting bit IENAD to 1, and A/D conversion is started by setting bit ADSF to 1. When A/D conversion is completed, bit IRRAD is set to 1, and the A/D conversion result is stored in ADRRH and ADRRL. At the same time bit ADSF is cleared to 0, and the A/D converter goes to the idle state. Bit IENAD = 1, so an A/D conversion end interrupt is requested. The A/D interrupt handling routine starts. The A/D conversion result is read and processed. The A/D interrupt handling routine ends. 2. 3. 4. 5. 6. If bit ADSF is set to 1 again afterward, A/D conversion starts and steps 2 through 6 take place. Figures 12.3 and 12.4 show flowcharts of procedures for using the A/D converter. Rev. 1.00 Dec. 13, 2007 Page 278 of 380 REJ09B0430-0100 Interrupt (IRRAD) Set* IENAD A/D conversion starts Set* Set* ADSF Channel 1 (AN1) operating state Idle A/D conversion (1) Idle Read conversion result A/D conversion result (1) A/D conversion (2) Idle Read conversion result A/D conversion result (2) ADRRH ADRRL Figure 12.2 Example of A/D Conversion Operation Note: * indicates instruction execution by software. Section 12 A/D Converter Rev. 1.00 Dec. 13, 2007 Page 279 of 380 REJ09B0430-0100 Section 12 A/D Converter Start Set A/D conversion speed and input channel Disable A/D conversion end interrupt Start A/D conversion Read ADSR No ADSF = 0? Yes Read ADRRH/ADRRL data Yes Perform A/D conversion? No End Figure 12.3 Flowchart of Procedure for Using A/D Converter (Polling by Software) Start Set A/D conversion speed and input channel Enable A/D conversion end interrupt Start A/D conversion A/D conversion end interrupt generated? No Yes Clear IRRAD bit in IRR2 to 0 Read ADRRH/ADRRL data Yes Perform A/D conversion? No End Figure 12.4 Flowchart of Procedure for Using A/D Converter (Interrupts Used) Rev. 1.00 Dec. 13, 2007 Page 280 of 380 REJ09B0430-0100 Section 12 A/D Converter 12.6 A/D Conversion Accuracy Definitions This LSI's A/D conversion accuracy definitions are given below. * Resolution The number of A/D converter digital output codes * Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 12.5). * Offset error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from the minimum voltage value 0000000000 to 0000000001 (see figure 12.6). * Full-scale error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from 1111111110 to 1111111111 (see figure 12.6). * Nonlinearity error The error with respect to the ideal A/D conversion characteristics between zero voltage and full-scale voltage. Does not include offset error, full-scale error, or quantization error. * Absolute accuracy The deviation between the digital value and the analog input value. Includes offset error, fullscale error, quantization error, and nonlinearity error. Rev. 1.00 Dec. 13, 2007 Page 281 of 380 REJ09B0430-0100 Section 12 A/D Converter Digital output 111 110 101 100 011 010 001 000 1 8 Ideal A/D conversion characteristic Quantization error 2 8 3 8 4 8 5 8 6 8 7 FS 8 Analog input voltage Figure 12.5 A/D Conversion Accuracy Definitions (1) Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic FS Analog input voltage Offset error Figure 12.6 A/D Conversion Accuracy Definitions (2) Rev. 1.00 Dec. 13, 2007 Page 282 of 380 REJ09B0430-0100 Section 12 A/D Converter 12.7 12.7.1 Usage Notes Permissible Signal Source Impedance This LSI's analog input is designed such that conversion accuracy is guaranteed for an input signal for which the signal source impedance is 10 k or less. This specification is provided to enable the A/D converter's sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 10 k, charging may be insufficient and it may not be possible to guarantee A/D conversion accuracy. As a countermeasure, a large capacitance can be provided externally to the analog input pin. This will cause the actual input resistance to comprise only the internal input resistance of 10 k , the signal source impedance does not need to be taken into consideration. This countermeasure has the disadvantage of creating a low-pass filter from the signal source impedance and capacitance, with the result that it may not be possible to follow analog signals having a large differential coefficient (e.g., 5 mV/s or greater) (see figure 12.7). When converting a high-speed analog signal, a lowimpedance buffer should be inserted. 12.7.2 Influences on Absolute Accuracy Adding capacitance results in coupling with GND, and therefore noise in GND may adversely affect absolute accuracy. Be sure to make the connection to an electrically stable GND. Care is also required to ensure that filter circuits do not interfere with digital signals or act as antennas on the mounting board. This LSI Sensor output impedance to 10 k Sensor input Low-pass filter C to 0.1 F Cin = 15 pF A/D converter equivalent circuit 10 k 20 pF Figure 12.7 Example of Analog Input Circuit Rev. 1.00 Dec. 13, 2007 Page 283 of 380 REJ09B0430-0100 Section 12 A/D Converter 12.7.3 1. 2. 3. 4. Additional Usage Notes ADRRH and ADRRL should be read only when the ADSF bit in ADSR is cleared to 0. Changing the digital input signal at an adjacent pin during A/D conversion may adversely affect conversion accuracy. When A/D conversion is started after clearing module standby mode, wait for 10 clock cycles before starting A/D conversion. In active mode and sleep mode, the analog power supply current flows in the ladder resistance even when the A/D converter is on standby. Therefore, if the A/D converter is not used, it is recommended that AVcc be connected to the system power supply and the ADCKSTP bit be cleared to 0 in CKSTPR1. Rev. 1.00 Dec. 13, 2007 Page 284 of 380 REJ09B0430-0100 Section 13 List of Registers Section 13 List of Registers The register list gives information on the on-chip I/O register addresses, how the register bits are configured, and the register states in each operating mode. The information is given as shown below. 1. * * * * 2. * * * Register addresses (address order) Registers are listed from the lower allocation addresses. Registers are classified by functional modules. The data bus width is indicated. The number of access states is indicated. Register bits Bit configurations of the registers are described in the same order as the register addresses. Reserved bits are indicated by in the bit name column. When registers consist of 16 bits, bits are described from the MSB side. 3. Register states in each operating mode * Register states are described in the same order as the register addresses. * The register states described here are for the basic operating modes. If there is a specific reset for an on-chip peripheral module, refer to the section on that on-chip peripheral module. Rev. 1.00 Dec. 13, 2007 Page 285 of 380 REJ09B0430-0100 Section 13 List of Registers 13.1 Register Addresses (Address Order) The data bus width indicates the numbers of bits by which the register is accessed. The number of access states indicates the number of states based on the specified reference clock. Register Name Flash memory control register 1 Flash memory control register 2 Flash memory power control register Erase block register Flash memory enable register Event counter PWM compare register H Event counter PWM compare register L Event counter PWM data register H Event counter PWM data register L Wakeup edge select register Serial port control register Input pin edge select register Event counter control register Event counter control/status register Event counter H Event counter L Serial mode register Bit rate register Serial control register 3 Transmit data register Serial status register Receive data register Abbreviation FLMCR1 FLMCR2 FLPWCR EBR FENR Module Bit No Address Name 8 8 8 8 8 H'F020 H'F021 H'F022 H'F023 H'F02B H'FF8C H'FF8D H'FF8E H'FF8F H'FF90 H'FF91 H'FF92 H'FF94 H'FF95 H'FF96 H'FF97 H'FFA8 H'FFA9 H'FFAA H'FFAB H'FFAC H'FFAD ROM ROM ROM ROM ROM AEC*1 AEC*1 AEC*1 AEC*1 Interrupts SCI3 AEC*1 AEC* AEC*1 1 Data Bus Access Width State 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 ECPWCRH 8 ECPWCRL 8 ECPWDRH 8 ECPWDRL 8 WEGR SPCR AEGSR ECCR ECCSR ECH ECL SMR BRR SCR3 TDR SSR RDR 8 8 8 8 8 8 8 8 8 8 8 8 8 AEC*1 AEC*1 SCI3 SCI3 SCI3 SCI3 SCI3 SCI3 Rev. 1.00 Dec. 13, 2007 Page 286 of 380 REJ09B0430-0100 Section 13 List of Registers Register Name Timer mode register A Timer counter A Timer control/status register W Timer counter W Timer control register F Timer control status register F 8-bit timer counter FH 8-bit timer counter FL Output compare register FH Output compare register FL A/D result register H A/D result register L A/D mode register A/D start register Port mode register 2 Port mode register 3 Port mode register 5 PWM2 control register PWM2 data register U PWM2 data register L PWM1 control register PWM1 data register U PWM1 data register L Port data register 3 Port data register 4 Port data register 5 Port data register 6 Port data register 7 Port data register 8 Port data register 9 Port data register A Abbreviation TMA TCA TCSRW TCW TCRF TCSRF TCFH TCFL OCRFH OCRFL ADRRH ADRRL AMR ADSR PMR2 PMR3 PMR5 PWCR2 PWDRU2 PWDRL2 PWCR1 PWDRU1 PWDRL1 PDR3 PDR4 PDR5 PDR6 PDR7 PDR8 PDR9 PDRA Module Bit No Address Name 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FFB0 H'FFB1 H'FFB2 H'FFB3 H'FFB6 H'FFB7 H'FFB8 H'FFB9 H'FFBA H'FFBB H'FFC4 H'FFC5 H'FFC6 H'FFC7 H'FFC9 H'FFCA H'FFCC H'FFCD H'FFCE H'FFCF H'FFD0 H'FFD1 H'FFD2 H'FFD6 H'FFD7 H'FFD8 H'FFD9 H'FFDA H'FFDB H'FFDC H'FFDD Timer A Timer A WDT*2 WDT* 2 Data Bus Access Width State 8 8 8 8 8 8 8 8 8 8 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Timer F Timer F Timer F Timer F Timer F Timer F A/D converter 8 A/D converter 8 A/D converter 8 A/D converter 8 I/O port I/O port I/O port 10-bit PWM 10-bit PWM 10-bit PWM 10-bit PWM 10-bit PWM 10-bit PWM I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Rev. 1.00 Dec. 13, 2007 Page 287 of 380 REJ09B0430-0100 Section 13 List of Registers Register Name Port data register B Port pull-up control register 3 Port pull-up control register 5 Port pull-up control register 6 Port control register 3 Port control register 4 Port control register 5 Port control register 6 Port control register 7 Port control register 8 Port mode register 9 Port control register A Port mode register B System control register 1 System control register 2 IRQ edge select register Interrupt enable register 1 Interrupt enable register 2 Interrupt request register 1 Interrupt request register 2 Abbreviation PDRB PUCR3 PUCR5 PUCR6 PCR3 PCR4 PCR5 PCR6 PCR7 PCR8 PMR9 PCRA PMRB SYSCR1 SYSCR2 IEGR IENR1 IENR2 IRR1 IRR2 Module Bit No Address Name 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FFDE H'FFE1 H'FFE2 H'FFE3 H'FFE6 H'FFE7 H'FFE8 H'FFE9 H'FFEA H'FFEB H'FFEC H'FFED H'FFEE H'FFF0 H'FFF1 H'FFF2 H'FFF3 H'FFF4 H'FFF6 H'FFF7 H'FFF9 H'FFFA H'FFFB I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port SYSTEM SYSTEM Interrupts Interrupts Interrupts Interrupts Interrupts Interrupts SYSTEM SYSTEM Data Bus Access Width State 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Wakeup interrupt request register IWPR Clock stop register 1 Clock stop register 2 CKSTPR1 8 CKSTPR2 8 Notes: 1. AEC: Asynchronous event counter 2. WDT: Watchdog timer Rev. 1.00 Dec. 13, 2007 Page 288 of 380 REJ09B0430-0100 Section 13 List of Registers 13.2 Register Bits Register bit names of the on-chip peripheral modules are described below. Register Abbreviation Bit 7 FLMCR1 FLMCR2 FLPWCR EBR FENR ECPWCRH ECPWCRL ECPWDRH ECPWDRL WEGR SPCR AEGSR ECCR ECCSR ECH ECL SMR BRR SCR3 TDR SSR RDR TMA TCA TCSRW TCW -- FLER PDWND -- FLSHE Bit 6 SWE -- -- -- -- Bit 5 ESU -- -- -- -- Bit 4 PSU -- -- EB4 -- Bit 3 EV -- -- EB3 -- Bit 2 PV -- -- EB2 -- Bit 1 E -- -- EB1 -- Bit 0 P -- -- EB0 -- 1 Module Name ROM ECPWCRH7 ECPWCRH6 ECPWCRH5 ECPWCRH4 ECPWCRH3 ECPWCRH2 ECPWCRH1 ECPWCRH0 AEC* ECPWCRL7 ECPWCRL6 ECPWCRL5 ECPWCRL4 ECPWCRL3 ECPWCRL2 ECPWCRL1 ECPWCRL0 ECPWDRH7 ECPWDRH6 ECPWDRH5 ECPWDRH4 ECPWDRH3 ECPWDRH2 ECPWDRH1 ECPWDRH0 ECPWDRL7 ECPWDRL6 ECPWDRL5 ECPWDRL4 ECPWDRL3 ECPWDRL2 ECPWDRL1 ECPWDRL0 WKEGS7 WKEGS6 WKEGS5 WKEGS4 WKEGS3 WKEGS2 WKEGS1 WKEGS0 Interrupts -- -- SPC32 -- SCINV3 SCINV2 AIEGS0 PWCK1 CUEL ECH2 ECL2 MP BRR2 TEIE TDR2 TEND RDR2 TMA2 TCA2 WDON TCW2 -- -- SCI3 1 AEC* AHEGS1 AHEGS0 ALEGS1 ALEGS0 AIEGS1 ACKH1 OVH ECH7 ECL7 COM BRR7 TIE TDR7 TDRE RDR7 -- TCA7 B6WI TCW7 ACKH0 OVL ECH6 ECL6 CHR BRR6 RIE TDR6 RDRF RDR6 -- TCA6 TCWE TCW6 ACKL1 -- ECH5 ECL5 PE BRR5 TE TDR5 OER RDR5 -- TCA5 B4WI TCW5 ACKL0 CH2 ECH4 ECL4 PM BRR4 RE TDR4 FER RDR4 -- TCA4 PWCK2 CUEH ECH3 ECL3 STOP BRR3 -- TDR3 PER RDR3 TMA3 TCA3 ECPWME -- PWCK0 CRCH ECH1 ECL1 CKS1 BRR1 CKE1 TDR1 MPBR RDR1 TMA1 TCA1 BOWI TCW1 -- CRCL ECH0 ECL0 CKS0 BRR0 CKE0 TDR0 MPBT RDR0 TMA0 TCA0 WRST TCW0 SCI3 Timer A WDT*2 TCSRWE B2WI TCW4 TCW3 Rev. 1.00 Dec. 13, 2007 Page 289 of 380 REJ09B0430-0100 Section 13 List of Registers Register Abbreviation Bit 7 TCRF TCSRF TCFH TCFL OCRFH OCRFL ADRRH ADRRL AMR ADSR PMR2 PMR3 PMR5 PWCR2 PWDRU2 PWDRL2 PWCR1 PWDRU1 PWDRL1 PDR3 PDR4 PDR5 PDR6 PDR7 PDR8 PDR9 PDRA PDRB PUCR3 PUCR5 PUCR6 PCR3 PCR4 TOLH OVFH TCFH7 TCFL7 Module Name Timer F Bit 6 CKSH2 CMFH TCFH6 TCFL6 Bit 5 CKSH1 OVIEH TCFH5 TCFL5 Bit 4 CKSH0 CCLRH TCFH4 TCFL4 Bit 3 TOLL OVFL TCFH3 TCFL3 Bit 2 CKSL2 CMFL TCFH2 TCFL2 Bit 1 CKSL1 OVIEL TCFH1 TCFL1 Bit 0 CKSL0 CCLRL TCFH0 TCFL0 OCRFH7 OCRFH6 OCRFH5 OCRFH4 OCRFH3 OCRFH2 OCRFH1 OCRFH0 OCRFL7 OCRFL6 OCRFL5 OCRFL4 OCRFL3 OCRFL2 OCRFL1 OCRFL0 ADR9 ADR1 CKS ADSF -- AEVL WKP7 -- -- ADR8 ADR0 -- -- -- AEVH WKP6 -- -- ADR7 -- -- -- POF1 -- WKP5 -- -- ADR6 -- -- -- -- -- WKP4 -- -- ADR5 -- CH3 -- -- -- WKP3 -- -- ADR4 -- CH2 -- WDCKS TMOFH WKP2 -- -- ADR3 -- CH1 -- -- TMOFL WKP1 ADR2 -- CH0 -- IRQ0 -- WKP0 I/O port A/D converter PWDRU21 PWDRU20 PWCR21 PWCR20 10-bit PWM PWDRL27 PWDRL26 PWDRL25 PWDRL24 PWDRL23 PWDRL22 PWDRL21 PWDRL20 -- -- -- -- -- -- -- -- -- -- -- -- PWCR11 PWCR10 PWDRU11 PWDRU10 PWDRL17 PWDRL16 PWDRL15 PWDRL14 PWDRL13 PWDRL12 PWDRL11 PWDRL10 P37 -- P57 P67 P77 -- -- -- -- P36 -- P56 P66 P76 -- -- -- -- P35 -- P55 P65 P75 -- P95 -- -- P34 -- P54 P64 P74 -- P94 -- -- P33 P43 P53 P63 P73 -- P93 PA3 PB3 P32 P42 P52 P62 P72 -- P92 PA2 PB2 P31 P41 P51 P61 P71 -- P91 PA1 PB1 -- P40 P50 P60 P70 P80 P90 PA0 PB0 I/O port PUCR37 PUCR36 PUCR35 PUCR34 PUCR33 PUCR32 PUCR31 -- PUCR57 PUCR56 PUCR55 PUCR54 PUCR53 PUCR52 PUCR51 PUCR50 PUCR67 PUCR66 PUCR65 PUCR64 PUCR63 PUCR62 PUCR61 PUCR60 PCR37 -- PCR36 -- PCR35 -- PCR34 -- PCR33 -- PCR32 PCR42 PCR31 PCR41 -- PCR40 Rev. 1.00 Dec. 13, 2007 Page 290 of 380 REJ09B0430-0100 Section 13 List of Registers Register Abbreviation Bit 7 PCR5 PCR6 PCR7 PCR8 PMR9 PCRA PMRB SYSCR1 SYSCR2 IEGR IENR1 IENR2 IRR1 IRR2 IWPR CKSTPR1 CKSTPR2 PCR57 PCR67 PCR77 -- -- -- -- SSBY -- -- IENTA IENDT IRRTA IRRDT IWPF7 -- -- Module Name I/O port Bit 6 PCR56 PCR66 PCR76 -- -- -- -- STS2 -- -- -- IENAD -- IRRAD IWPF6 -- -- Bit 5 PCR55 PCR65 PCR75 -- -- -- -- STS1 -- -- IENWP -- -- -- IWPF5 Bit 4 PCR54 PCR64 PCR74 -- -- -- -- STS0 NESEL -- -- -- -- -- IWPF4 Bit 3 PCR53 PCR63 PCR73 -- PIOFF PCRA3 IRQ1 LSON DTON -- -- IENTFH -- IRRTFH IWPF3 Bit 2 PCR52 PCR62 PCR72 -- -- PCRA2 -- -- MSON -- IENEC2 IENTFL IRREC2 IRRTFL IWPF2 Bit 1 PCR51 PCR61 PCR71 -- PWM2 PCRA1 -- MA1 SA1 IEG1 IEN1 -- IRRI1 -- IWPF1 Bit 0 PCR50 PCR60 PCR70 PCR80 PWM1 PCRA0 -- MA0 SA0 IEG0 IEN0 IENEC IRRI0 IRREC IWPF0 SYSTEM Interrupts Interrupts Interrupts S32CKSTP ADCKSTP -- TFCKSTP -- TACKSTP SYSTEM -- PW2CKSTP AECKSTP WDCKSTP PW1CKSTP -- Notes: 1. AEC: Asynchronous event counter 2. WDT: Watchdog timer Rev. 1.00 Dec. 13, 2007 Page 291 of 380 REJ09B0430-0100 Section 13 List of Registers 13.3 Register States in Each Operating Mode Active -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Sleep -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Watch Initialized -- -- Initialized -- -- -- -- -- -- -- -- -- -- -- -- Initialized Initialized Initialized Initialized Initialized Initialized -- -- -- -- Subactive Subsleep Standby Initialized -- -- Initialized -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Initialized -- -- Initialized -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Initialized -- -- Initialized -- -- -- -- -- -- -- -- -- -- -- -- Initialized Initialized Initialized Initialized Initialized Initialized -- -- -- -- 2 WDT* Register Abbreviation Reset FLMCR1 FLMCR2 FLPWCR EBR FENR ECPWCRH ECPWCRL ECPWDRH ECPWDRL WEGR SPCR AEGSR ECCR ECCSR ECH ECL SMR BRR SCR3 TDR SSR RDR TMA TCA TCSRW TCW Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Module ROM AEC* 1 Interrupts SCI3 AEC* 1 SCI3 Timer A Rev. 1.00 Dec. 13, 2007 Page 292 of 380 REJ09B0430-0100 Section 13 List of Registers Register Abbreviation Reset TCRF TCSRF TCFH TCFL OCRFH OCRFL ADRRH ADRRL AMR ADSR PMR2 PMR3 PMR5 PWCR2 PWDRU2 PWDRL2 PWCR1 PWDRU1 PWDRL1 PDR3 PDR4 PDR5 PDR6 PDR7 PDR8 PDR9 PDRA PDRB PUCR3 PUCR5 PUCR6 PCR3 PCR4 Initialized Initialized Initialized Initialized Initialized Initialized -- -- Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Active -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Sleep -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Watch -- -- -- -- -- -- -- -- -- Initialized -- -- -- -- -- -- -- -- -- -- -- Subactive Subsleep Standby -- -- -- -- -- -- -- -- -- Initialized -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Initialized -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Initialized -- -- -- -- -- -- -- -- -- -- -- Module Timer F A/D converter I/O port 10-bit PWM I/O port -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Rev. 1.00 Dec. 13, 2007 Page 293 of 380 REJ09B0430-0100 Section 13 List of Registers Register Abbreviation Reset PCR5 PCR6 PCR7 PCR8 PMR9 PCRA PMRB SYSCR1 SYSCR2 IEGR IENR1 IENR2 IRR1 IRR2 IWPR CKSTPR1 CKSTPR2 Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Active Sleep Watch Subactive Subsleep Standby Module I/O port -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- SYSTEM Interrupts SYSTEM Notes: is not initialized 1. AEC: Asynchronous event counter 2. WDT: Watchdog timer Rev. 1.00 Dec. 13, 2007 Page 294 of 380 REJ09B0430-0100 Section 14 Electrical Characteristics Section 14 Electrical Characteristics 14.1 Absolute Maximum Ratings of H8/38704 Group (Flash Memory Version, Mask ROM Version), H8/38702S Group (Mask ROM Version) Table 14.1 lists the absolute maximum ratings. Table 14.1 Absolute Maximum Ratings Item Power supply voltage Analog power supply voltage Input voltage Other than port B Port B Port 9 pin voltage Operating temperature Symbol VCC AVCC Vin AVin VP9 Topr Value -0.3 to +4.3 -0.3 to +4.3 -0.3 to VCC +0.3 -0.3 to AVCC +0.3 -0.3 to VCC +0.3 Regular specifications: -20 to +75*2 Wide-range temperature specifications: 3 -40 to +85* Storage temperature Tstg -55 to +125 C Notes: 1. Permanent damage may result if maximum ratings are exceeded. Normal operation should be under the conditions specified in Electrical Characteristics. Exceeding these values can result in incorrect operation and reduced reliability. 2. When the operating voltage is VCC = 2.7 to 3.6 V during flash memory reading, the operating temperature ranges from -20C to +75C when programming or erasing the flash memory. When the operating voltage is VCC = 2.2 to 3.6 V during flash memory reading, the operating temperature ranges from -20C to +50C when programming or erasing the flash memory. 3. The operating temperature ranges from -20C to +75C when programming or erasing the flash memory. Unit V V V V V C Note *1 Rev. 1.00 Dec. 13, 2007 Page 295 of 380 REJ09B0430-0100 Section 14 Electrical Characteristics 14.2 Electrical Characteristics of H8/38704 Group (Flash Memory Version, Mask ROM Version), H8/38702S Group (Mask ROM Version) Power Supply Voltage and Operating Ranges 14.2.1 (1) (a) Power Supply Voltage and Oscillation Frequency Range (Flash Memory Version) 4-MHz Specification 10.0 38.4 fosc (MHz) fw (kHz) 4.0 2.0 2.2 2.7 3.6 Vcc (V) 32.768 2.2 2.7 3.6 Vcc (V) * Active (high-speed) mode * Sleep (high-speed) mode * All operating modes (b) 10-MHz Specification 10.0 38.4 fosc (MHz) fw (kHz) 4.0 2.0 2.7 3.6 Vcc (V) 32.768 2.2 2.7 3.6 Vcc (V) * Active (high-speed) mode * Sleep (high-speed) mode * All operating modes Rev. 1.00 Dec. 13, 2007 Page 296 of 380 REJ09B0430-0100 Section 14 Electrical Characteristics (2) Power Supply Voltage and Oscillation Frequency Range (Mask ROM Version) 10.0 38.4 fosc (MHz) fw (kHz) 4.0 2.0 1.8 2.7 3.6 Vcc (V) 32.768 1.8 2.7 3.6 Vcc (V) * Active (high-speed) mode * Sleep (high-speed) mode * All operating modes * When a resonator is used, hold Vcc at 2.2 V to 3.6 V from power-on until the oscillation stabilization time has elapsed. Rev. 1.00 Dec. 13, 2007 Page 297 of 380 REJ09B0430-0100 Section 14 Electrical Characteristics (3) Power Supply Voltage and Operating Frequency Range (Flash Memory Version) 5.0 19.2 SUB (kHz) 2.0 1.0 2.2 2.7 3.6 Vcc (V) 16.384 9.6 8.192 4.8 4.096 (MHz) 2.2 2.7 * Active (high-speed) mode * Sleep (high-speed) mode (except CPU) * Subactive mode 3.6 Vcc (V) * Subsleep mode (except CPU) * Watch mode (except CPU) 625 (kHz) 250 15.625 2.2 2.7 3.6 Vcc (V) * Active (medium-speed) mode * Sleep (medium-speed) mode (except A/D converter) Rev. 1.00 Dec. 13, 2007 Page 298 of 380 REJ09B0430-0100 Section 14 Electrical Characteristics (4) Power Supply Voltage and Operating Frequency Range (Mask ROM Version) 5.0 19.2 SUB (kHz) 2.0 1.0 1.8 2.7 3.6 Vcc (V) 16.384 9.6 8.192 4.8 4.096 (MHz) 1.8 2.7 * Active (high-speed) mode * Sleep (high-speed) mode (except CPU) * Subactive mode 3.6 Vcc (V) * Subsleep mode (except CPU) * Watch mode (except CPU) 625 (kHz) 250 15.625 1.8 2.7 3.6 Vcc (V) * Active (medium-speed) mode * Sleep (medium-speed) mode (except A/D converter) Rev. 1.00 Dec. 13, 2007 Page 299 of 380 REJ09B0430-0100 Section 14 Electrical Characteristics (5) Analog Power Supply Voltage and A/D Converter Operating Range (Flash Memory Version) 5.0 (MHz) (kHz) 625 1.0 2.2 2.7 3.6 AVcc (V) 500 2.7 3.6 AVcc (V) * Active (high-speed) mode * Sleep (high-speed) mode * Active (medium-speed) mode * Sleep (medium-speed) mode Note: When AVcc = 2.2 V to 2.7 V, the operating range is limited to = 1.0 MHz. (6) Analog Power Supply Voltage and A/D Converter Operating Range (Mask ROM Version) 5.0 (MHz) (kHz) 625 1.0 1.8 2.7 3.6 AVcc (V) 500 2.7 3.6 AVcc (V) * Active (high-speed) mode * Sleep (high-speed) mode * Active (medium-speed) mode * Sleep (medium-speed) mode Note: When AVcc = 1.8 V to 2.7 V, the operating range is limited to = 1.0 MHz. Rev. 1.00 Dec. 13, 2007 Page 300 of 380 REJ09B0430-0100 Section 14 Electrical Characteristics 14.2.2 DC Characteristics Table 14.2 lists the DC characteristics. Table 14.2 DC Characteristics One of following conditions is applied unless otherwise specified. Condition A (Flash memory version): VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V Condition B (Flash memory version): VCC = 2.2 V to 3.6 V, AVCC = 2.2 V to 3.6 V, VSS = AVSS = 0.0 V Condition C (Mask ROM version): VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V Values Item Symbol Applicable Pins RES, WKP0 to WKP7, IRQ0, AEVL, AEVH, SCK32 IRQ1 RXD32 OSC1 X1 P31 to P37, P40 to P43, P50 to P57, P60 to P67, P70 to P77, P80, PA0 to PA3 PB0 to PB3 IRQAEC, P95* 5 Test Condition Min. VCC x 0.9 Typ. -- Max. VCC + 0.3 Unit V Notes Input high VIH voltage VCC x 0.9 VCC x 0.8 VCC x 0.9 VCC = 1.8 V to 3.6 V VCC x 0.9 VCC x 0.8 -- -- -- -- -- AVCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 V V V V V VCC x 0.8 VCC x 0.9 -- -- AVCC + 0.3 VCC + 0.3 V V Rev. 1.00 Dec. 13, 2007 Page 301 of 380 REJ09B0430-0100 Section 14 Electrical Characteristics Values Item Input low voltage Symbol VIL Applicable Pins RES, WKP0 to WKP7, IRQ0, IRQ1, 5 IRQAEC, P95* , AEVL, AEVH, SCK32 RXD32 OSC1 X1 P31 to P37, P40 to P43, P50 to P57, P60 to P67, P70 to P77, P80, PA0 to PA3, PB0 to PB3 Output high voltage VOH P31 to P37, P40 to P42, P50 to P57, P60 to P67, P70 to P77, P80, PA0 to PA3 P40 to P42, P50 to P57, P60 to P67, P70 to P77, P80, PA0 to PA3, P31 to P37 P90 to P95 VCC = 2.7 V to 3.6 V -IOH = 1.0 mA -IOH = 0.1 mA VCC - 0.3 -- -- Test Condition Min. - 0.3 Typ. -- Max. Unit Notes VCC x 0.1 V - 0.3 - 0.3 - 0.3 - 0.3 -- -- -- -- VCC x 0.2 V VCC x 0.1 V VCC x 0.1 V VCC x 0.2 V VCC - 1.0 -- -- V Output low VOL voltage IOL = 0.4 mA -- -- 0.5 V VCC = 2.2 V to 3.6 V IOL = 10.0 mA VCC = 1.8 V to 3.6 V IOL = 8.0 mA -- -- 0.5 Rev. 1.00 Dec. 13, 2007 Page 302 of 380 REJ09B0430-0100 Section 14 Electrical Characteristics Values Item Input/ output leakage current Symbol | IIL | Applicable Pins RES, P43, OSC1, X1, P31 to P37, P40 to P42, P50 to P57, P60 to P67, P70 to P77, P80, IRQAEC, PA0 to PA3, P90 to P95 PB0 to PB3 Pull-up MOS current Input capacitance Vcc start voltage -Ip P31 to P37, P50 to P57, P60 to P67 All input pins except power supply pin VCC VCC Test Condition VIN = 0.5 V to VCC - 0.5 V Min. -- Typ. -- Max. 1.0 Unit A Notes VIN = 0.5 V to AVCC - -- 0.5 V VCC = 3.0 V, VIN = 0.0 V f = 1 MHz, VIN = 0.0 V, Ta = 25C 30 -- -- 1.0 180 A Cin -- -- 15.0 pF VccSTART 0 0.05 -- -- 0.1 -- V V/ms *2 *2 Vcc rising SVCC slope Rev. 1.00 Dec. 13, 2007 Page 303 of 380 REJ09B0430-0100 Section 14 Electrical Characteristics Values Item Active mode supply current Symbol IOPE1 Applicable Pins VCC Test Condition Active (high-speed) mode VCC = 1.8 V, fOSC = 2 MHz Active (high-speed) mode VCC = 3 V, fOSC = 2 MHz Min. -- Typ. 0.4 Max. -- Unit mA Notes *1*3*4 Approx. max. value = 1.1 x Typ. -- 0.6 -- *1*3*4 Approx. max. value = 1.1 x Typ. *2*3*4 Approx. max. value = 1.1 x Typ. Active (high-speed) mode VCC = 3 V, fOSC = 4 MHz -- 1.2 -- *1*3*4 Approx. max. value = 1.1 x Typ. *2*3*4 Condition B *1*3*4 *2*3*4 Condition A -- 1.0 -- -- 1.6 2.8 Active (high-speed) mode VCC = 3 V, fOSC = 10 MHz -- -- 3.1 3.6 6.0 6.0 Rev. 1.00 Dec. 13, 2007 Page 304 of 380 REJ09B0430-0100 Section 14 Electrical Characteristics Values Item Active mode supply current Symbol IOPE2 Applicable Pins VCC Test Condition Active (mediumspeed) mode VCC = 1.8 V, fOSC = 2 MHz, OSC/128 Active (mediumspeed) mode VCC = 3 V, fOSC = 2 MHz, OSC/128 Min. -- Typ. 0.06 Max. -- Unit Notes *1*3*4 Approx. max. value = 1.1 x Typ. -- 0.1 -- *1*3*4 Approx. max. value = 1.1 x Typ. *2*3*4 Approx. max. value = 1.1 x Typ. Active (mediumspeed) mode VCC = 3 V, fOSC = 4 MHz, OSC/128 -- 0.2 -- *1*3*4 Approx. max. value = 1.1 x Typ. *2*3*4 Condition B *1*3*4 *2*3*4 Condition A -- 0.5 -- -- 0.7 1.3 Active (mediumspeed) mode VCC = 3 V, fOSC = 10 MHz, OSC/128 -- -- 0.6 1.0 1.8 1.8 Rev. 1.00 Dec. 13, 2007 Page 305 of 380 REJ09B0430-0100 Section 14 Electrical Characteristics Values Item Sleep mode supply current Symbol ISLEEP Applicable Pins VCC Test Condition VCC = 1.8 V, fOSC = 2 MHz Min. -- Typ. 0.16 Max. -- Unit mA Notes *1*3*4 Approx. max. value = 1.1 x Typ. -- 0.3 -- *1*3*4 Approx. max. value = 1.1 x Typ. *2*3*4 Approx. max. value = 1.1 x Typ. VCC = 3 V, fOSC = 4 MHz -- 0.5 -- *1*3*4 Approx. max. value = 1.1 x Typ. *2*3*4 Condition B *1*3*4 *2*3*4 Condition A VCC = 3 V, fOSC = 2 MHz -- 0.6 -- -- 0.9 2.2 VCC = 3 V, fOSC = 10 MHz -- -- 1.3 1.7 4.8 4.8 Rev. 1.00 Dec. 13, 2007 Page 306 of 380 REJ09B0430-0100 Section 14 Electrical Characteristics Values Item Symbol Applicable Pins VCC Test Condition VCC = 1.8 V, 32-kHz external clock input (SUB = W/2) VCC = 1.8 V, 32-kHz crystal resonator used (SUB = W/2) VCC = 2.7 V, 32-kHz external clock input (SUB = W/2) VCC = 2.7 V, 32-kHz crystal resonator used (SUB = W/2) VCC = 2.7 V, 32-kHz external clock input (SUB = W/2) VCC = 2.7 V, 32-kHz crystal resonator used (SUB = W/2) Subsleep mode supply current ISUBSP VCC VCC = 2.7 V, 32-kHz external clock input (SUB = W/2) VCC = 2.7 V, 32-kHz crystal resonator used (SUB = W/2) Min. -- Typ. 6.2 Max. -- Unit A Notes *1*3*4 Reference value Subactive ISUB mode supply current -- 5.4 -- -- 10 40 *1*3*4 -- 11 40 -- 28 50 *2*3*4 -- 25 50 -- 4.6 16 A *3*4 -- 5.1 16 Rev. 1.00 Dec. 13, 2007 Page 307 of 380 REJ09B0430-0100 Section 14 Electrical Characteristics Values Item Watch mode supply current Symbol IWATCH Applicable Pins VCC Test Condition VCC = 1.8 V, Ta = 25C, 32-kHz external clock input VCC = 1.8 V, Ta = 25C, 32-kHz crystal resonator used VCC = 2.7 V, Ta = 25C, 32-kHz external clock input VCC = 2.7 V, Ta = 25C, 32-kHz crystal resonator used VCC = 2.7 V, 32-kHz external clock input VCC = 2.7 V, 32-kHz crystal resonator used Standby mode supply current ISTBY VCC VCC = 1.8 V, Ta = 25C, 32-kHz crystal resonator not used VCC = 3.0 V, Ta = 25C, 32-kHz crystal resonator not used 32-kHz crystal resonator not used RAM data VRAM retaining voltage VCC Min. -- Typ. 1.2 Max. -- Unit A Notes *1*3*4 Reference value -- 0.6 -- -- 2.0 -- *3*4 Reference value -- 2.9 -- -- 2.0 6.0 *3*4 -- 2.9 6.0 -- 0.1 -- A *1*3*4 Reference value -- 0.3 -- *3*4 Reference value -- 1.5 1.0 -- 5.0 -- V *3*4 Rev. 1.00 Dec. 13, 2007 Page 308 of 380 REJ09B0430-0100 Section 14 Electrical Characteristics Values Item Symbol Applicable Pins Output pins except port 9 P90 to P95 VCC = 2.2 V to 3.6 V Other than above Allowable IOL output low current (total) Allowable -IOH output high current (per pin) Allowable -IOH output high current (total) Output pins except port 9 Port 9 All output pins VCC = 2.7 V to 3.6 V Other than above Test Condition Min. -- -- -- -- -- -- -- Typ. -- -- -- -- -- -- -- Max. 0.5 10.0 8.0 20.0 60.0 2.0 0.2 mA mA Item mA Symbol Allowable IOL output low current (per pin) All output pins -- -- 10.0 mA Rev. 1.00 Dec. 13, 2007 Page 309 of 380 REJ09B0430-0100 Section 14 Electrical Characteristics Notes: Connect the TEST pin to VSS. 1. Applies to the mask-ROM version. 2. Applies to the flash memory version. 3. Pin states when supply current is measured Mode Active (high-speed) mode (IOPE1) Active (medium-speed) mode (IOPE2) Sleep mode Subactive mode Subsleep mode VCC VCC VCC Only all on-chip timers operate Only CPU operates Only all on-chip timers operate CPU stops Watch mode VCC Only clock time base operates CPU stops Standby mode VCC CPU and timers both stop VCC System clock: crystal resonator Subclock: Pin X1 = GND VCC VCC VCC VCC System clock: crystal resonator Subclock: crystal resonator RES Pin VCC Internal State Only CPU operates Other Pins VCC Oscillator Pins System clock: crystal resonator Subclock: Pin X1 = GND 4. Except current which flows to the pull-up MOS or output buffer 5. Used when user mode or boot mode is determined after canceling a reset in the flash memory version Rev. 1.00 Dec. 13, 2007 Page 310 of 380 REJ09B0430-0100 Section 14 Electrical Characteristics 14.2.3 AC Characteristics Table 14.3 lists the control signal timing and table 14.4 lists the serial interface timing. Table 14.3 Control Signal Timing One of following conditions is applied unless otherwise specified. Condition A (Flash memory version): VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V Condition B (Flash memory version): VCC = 2.2 V to 3.6 V, AVCC = 2.2 V to 3.6 V, VSS = AVSS = 0.0 V Condition C (Mask ROM version): VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V Values Test Condition Min. Typ. -- Max. 10.0 Unit MHz Reference Figure Item System clock oscillation frequency Symbol fOSC Applicable Pins OSC1, OSC2 VCC = 2.7 V to 3.6 V 2.0 in conditions A and C Other than above in 2.0 condition C and condition B -- 4.0 OSC clock (OSC) cycle time tOSC OSC1, OSC2 VCC = 2.7 V to 3.6 V 100 in conditions A and C Other than above in 250 condition C and condition B -- 500 ns Figure 14.1 -- 500 System clock () cycle time tcyc X1, X2 X1, X2 2 -- -- -- 2 2 -- -- 32.768 or 38.4 30.5 or 26.0 -- -- 128 64 -- -- 8 -- tOSC s kHz s tW tcyc tsubcyc Figure 14.1 * Subclock oscillation fW frequency Watch clock (W) cycle time Subclock (SUB) cycle time Instruction cycle time tW tsubcyc Rev. 1.00 Dec. 13, 2007 Page 311 of 380 REJ09B0430-0100 Section 14 Electrical Characteristics Values Test Condition Min. Typ. 0.8 Max. 2.0 Unit ms Item Oscillation stabilization time Symbol trc Applicable Pins OSC1, OSC2 Reference Figure Figure 14.8 VCC = 2.7 V to 3.6 V -- when using crystal resonator in figure 14.8 VCC = 2.2 V to 3.6 V -- when using crystal resonator in figure 14.8 and in conditions B and C Other than above in -- condition C and when using crystal resonator in figure 14.8 VCC = 2.7 V to 3.6 V -- when using ceramic resonator in figure 14.8 and in conditions A and C VCC = 2.2 V to 3.6 V -- when using ceramic resonator (1) in figure 14.8 and in conditions B and C Other than above in -- condition C and when using ceramic resonator (1) in figure 14.8 Other than above -- 1.2 3.0 4.0 -- 20 45 s 20 45 80 -- -- -- -- 50 2.0 2.0 ms s trc X1, X2 VCC = 2.7 V to 3.6 V -- VCC = 2.2 V to 3.6 V -- and in conditions B and C Other than above in -- condition C 4.0 -- Rev. 1.00 Dec. 13, 2007 Page 312 of 380 REJ09B0430-0100 Section 14 Electrical Characteristics Values Test Condition VCC = 2.7 V to 3.6 V in conditions A and C Other than above in condition C and condition B X1 External clock low width tCPL OSC1 VCC = 2.7 V to 3.6 V in conditions A and C Other than above in condition C and condition B X1 External clock rise time tCPr OSC1 VCC = 2.7 V to 3.6 V in conditions A and C Other than above in condition C and condition B X1 External clock fall time tCPf OSC1 VCC = 2.7 V to 3.6 V in conditions A and C Other than above in condition C and condition B X1 RES pin low width Input pin high width tREL tIH RES IRQ0, IRQ1, IRQAEC, WKP0 to WKP7, AEVL, AEVH Min. 40 Typ. -- Max. -- Unit ns Item Symbol Applicable Pins OSC1 Reference Figure Figure 14.1 External clock high tCPH width 100 -- -- -- 40 15.26 or -- 13.02 -- -- s ns Figure 14.1 100 -- -- -- -- 15.26 or -- 13.02 -- 10 s ns Figure 14.1 -- -- 25 -- -- -- -- 55.0 10 ns ns Figure 14.1 -- -- 25 -- 10 2 -- -- -- 55.0 -- -- ns tcyc tcyc tsubcyc Figure 14.2 Figure 14.3 0.5 -- -- tOSC Rev. 1.00 Dec. 13, 2007 Page 313 of 380 REJ09B0430-0100 Section 14 Electrical Characteristics Item Input pin low width Applicable Symbol Pins Test Condition tIL IRQ0, IRQ1, IRQAEC, WKP0 to WKP7, AEVL, AEVH Values Min. 2 Typ. -- Max. -- Unit tcyc tsubcyc Reference Figure Figure 14.3 0.5 -- -- tOSC Note: * Determined by the SA1 and SA0 bits in the system control register 2 (SYSCR2). Table 14.4 Serial Interface (SCI3) Timing One of following conditions is applied unless otherwise specified. Condition A (Flash memory version): VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V Condition B (Flash memory version): VCC = 2.2 V to 3.6 V, AVCC = 2.2 V to 3.6 V, VSS = AVSS = 0.0 V Condition C (Mask ROM version): VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V Test Condition Values Min. 4 6 tSCKW tTXD tRXS tRXH 0.4 -- 400.0 400.0 Typ. Max. Unit -- -- -- -- -- -- -- -- 0.6 1 -- -- tscyc Figure 14.4 Reference Figure Item Input clock Asynchronous cycle Clocked synchronous Input clock pulse width Transmit data delay time (clocked synchronous) Receive data setup time (clocked synchronous) Receive data hold time (clocked synchronous) Symbol tscyc tcyc or tsubcyc Figure 14.4 tcyc or tsubcyc Figure 14.5 ns ns Figure 14.5 Figure 14.5 Rev. 1.00 Dec. 13, 2007 Page 314 of 380 REJ09B0430-0100 Section 14 Electrical Characteristics 14.2.4 A/D Converter Characteristics Table 14.5 shows the A/D converter characteristics. Table 14.5 A/D Converter Characteristics One of following conditions is applied unless otherwise specified. Condition A (Flash memory version): VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V Condition B (Flash memory version): VCC = 2.2 V to 3.6 V, AVCC = 2.2 V to 3.6 V, VSS = AVSS = 0.0 V Condition C (Mask ROM version): VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V Values Min. 2.7 2.2 1.8 - 0.3 AVCC = 3.0 V -- -- Typ. -- -- -- -- -- 600 Max. 3.6 3.6 3.6 AVCC + 0.3 V 1.0 -- mA A *2 Reference value *3 Unit V Reference Figure *1 Item Symbol Applicable Test Pins Condition AVCC Condition A Condition B Condition C Analog power supply AVCC voltage Analog input voltage AVIN AN0 to AN3 AVCC AVCC Analog power supply AIOPE current AISTOP1 AISTOP2 Analog input capacitance Allowable signal source impedance Resolution (data length) CAIN RAIN AVCC AN0 to AN3 -- -- -- -- -- -- -- -- 5.0 15.0 10.0 10 A pF k bit Rev. 1.00 Dec. 13, 2007 Page 315 of 380 REJ09B0430-0100 Section 14 Electrical Characteristics Values Min. -- -- Typ. -- -- Max. 3.5 5.5 Unit LSB Item Nonlinearity error Symbol Applicable Test Pins Condition AVCC = 2.7 V to 3.6 V AVCC = 2.2 V to 3.6 V in condition B, AVCC = 2.0 V to 3.6 V in condition C Other than above in condition C Reference Figure -- -- 7.5 *4 Quantization error Absolute accuracy AVCC = 2.7 V to 3.6 V AVCC = 2.2 V to 3.6 V in condition B, AVCC = 2.0 V to 3.6 V in condition C Other than above in condition C Conversion time AVCC = 2.7 V to 3.6 V Other than above -- -- -- -- 2.0 2.5 0.5 4.0 6.0 LSB LSB -- 2.5 8.0 *4 12.4 62 -- -- 124 124 s Notes: 1. Set AVCC = VCC when the A/D converter is not used. 2. AISTOP1 is the current in active and sleep modes while the A/D converter is idle. 3. AISTOP2 is the current at reset and in standby, watch, subactive, and subsleep modes while the A/D converter is idle. 4. The conversion time is 62 s. Rev. 1.00 Dec. 13, 2007 Page 316 of 380 REJ09B0430-0100 Section 14 Electrical Characteristics 14.2.5 Flash Memory Characteristics Table 14.6 shows the flash memory characteristics. Table 14.6 Flash Memory Characteristics Condition A: AVCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, VCC = 2.7 V to 3.6 V (range of operating voltage when reading), VCC = 3.0 V to 3.6 V (range of operating voltage when programming/erasing), Ta = -20C to +75C (range of operating temperature when programming/erasing: product with regular specifications, product with wide-range temperature specifications) AVCC = 2.2 V to 3.6 V, VSS = AVSS = 0.0 V, VCC = 2.2 V to 3.6 V (range of operating voltage when reading), VCC = 3.0 V to 3.6 V (range of operating voltage when programming/erasing), Ta = -20C to +50C (range of operating temperature when programming/erasing: product with regular specifications) Test Conditions Values Min. -- -- Typ. 7 100 Max. Unit 200 ms/ 128 bytes Condition B: Item Programming time*1*2*4 Erase time*1*3*5 Reprogramming count Data retain period Programming Wait time after SWE-bit setting*1 Wait time after 1 PSU-bit setting* Wait time after 14 P-bit setting* * Symbol tP tE NWEC tDRP x y z1 z2 z3 Wait time after 1 P-bit clear* Wait time after 1 PSU-bit clear* Wait time after PV-bit setting*1 1200 ms/ block times year s s s s s s s s 1000*8 10000*9 -- 10*10 -- -- 1 50 1n6 7 n 1000 28 198 -- -- 30 200 10 -- -- -- -- -- 32 202 12 -- -- -- Additional 8 programming 5 5 4 Rev. 1.00 Dec. 13, 2007 Page 317 of 380 REJ09B0430-0100 Section 14 Electrical Characteristics Item Programming Wait time after 1 dummy write* Wait time after PV-bit clear*1 Wait time after 1 SWE-bit clear* Maximum programming count*1*4*5 Erase Wait time after 1 SWE-bit setting* Wait time after ESU-bit setting*1 Wait time after 16 E-bit setting* * Wait time after 1 E-bit clear* Wait time after ESU-bit clear*1 Wait time after 1 EV-bit setting* Wait time after 1 dummy write* Wait time after EV-bit clear*1 Wait time after 1 SWE-bit clear* Maximum erase 167 count* * * Notes: Symbol N Test Conditions Values Min. 2 2 100 -- Typ. -- -- -- -- Max. Unit -- -- -- s s s 1000 times x y z N 1 100 10 10 10 20 2 4 100 -- -- -- -- -- -- -- -- -- -- -- -- -- 100 -- -- -- -- -- -- 120 s s ms s s s s s s times 1. Set the times according to the program/erase algorithms. 2. Programming time per 128 bytes (Shows the total period for which the P bit in FLMCR1 is set. It does not include the programming verification time.) 3. Block erase time (Shows the total period for which the E bit in FLMCR1 is set. It does not include the erase verification time.) 4. Maximum programming time (tP (max)) tP (max) = Wait time after P-bit setting (z) * maximum number of writes (N) 5. The maximum number of writes (N) should be set according to the actual set value of z1, z2, and z3 to allow programming within the maximum programming time (tP (max)). The wait time after P-bit setting (z1 and z2) should be alternated according to the number of writes (n) as follows: 1n6 z1 = 30 s 7 n 1000 z2 = 200 s Rev. 1.00 Dec. 13, 2007 Page 318 of 380 REJ09B0430-0100 Section 14 Electrical Characteristics 6. Maximum erase time (tE (max)) tE (max) = Wait time after E-bit setting (z) * maximum erase count (N) 7. The maximum number of erases (N) should be set according to the actual set value of z to allow erasing within the maximum erase time (tE (max)). 8. This minimum value guarantees all characteristics after reprogramming (the guaranteed range is from 1 to the minimum value). 9. Reference value when the temperature is 25C (normally reprogramming will be performed by this count). 10. This is a data retain characteristic when reprogramming is performed within the specification range including this minimum value. 14.3 Operation Timing Figures 14.1 to 14.5 show the operation timings. tOSC, tW OSC1, X1 VIH VIL tCPH tcpr tCPL tCPf Figure 14.1 Clock Input Timing RES VIL tREL Figure 14.2 RES Low Width Timing IRQ0, IRQ1, WKP0 to WKP7, IRQAEC, AEVL, AEVH VIH VIL tIL tIH Figure 14.3 Input Timing Rev. 1.00 Dec. 13, 2007 Page 319 of 380 REJ09B0430-0100 Section 14 Electrical Characteristics tSCKW SCK32 tscyc Figure 14.4 SCK3 Input Clock Timing tscyc SCK32 VIH or VOH* VIL or VOL* tTXD TXD32 (transmit data) VOH* VOL* tRXS tRXH RXD32 (receive data) Note: * Output timing reference levels Output high Output low VOH = 1/2 VCC + 0.2 V VOL = 0.8 V Load conditions are shown in figure 14.6. Figure 14.5 SCI3 Input/Output Timing in Clocked Synchronous Mode Rev. 1.00 Dec. 13, 2007 Page 320 of 380 REJ09B0430-0100 Section 14 Electrical Characteristics 14.4 Output Load Condition VCC 2.4 k LSI output pin 30 pF 12 k Figure 14.6 Output Load Circuit 14.5 Resonator Equivalent Circuit LS CS RS OSC1 CO OSC2 Crystal Resonator Parameter Frequency (MHz) RS (max.) CO (max.) 4 4.193 10 Ceramic Resonator Parameter Frequency (MHz) RS (max.) CO (max.) 2 18.3 4 6.8 10 4.6 100 100 30 16 pF 16 pF 16 pF 36.94 pF 36.72 pF 32.31 pF Figure 14.7 Resonator Equivalent Circuit Rev. 1.00 Dec. 13, 2007 Page 321 of 380 REJ09B0430-0100 Section 14 Electrical Characteristics LS CS RS OSC1 CO OSC2 Crystal Resonator Parameter (Nominal Values by Manufacturer) Frequency Rs (max) Co (max) Ceramic Resonator Parameter (1) (Nominal Values by Manufacturer) Frequency Rs (max) Co (max) 4 150 12pF Manufacturer KYOCERA KINSEKI CORPORATION 2 18.3 Manufacturer Murata Manufacturing 36.94pF Co., Ltd. Ceramic Resonator Parameter (2) (Nominal Values by Manufacturer) Frequency Rs (max) Co (max) 10 4.6 Manufacturer Murata Manufacturing 32.31pF Co., Ltd. Figure 14.8 Resonator Equivalent Circuit 14.6 Usage Note The flash memory and mask ROM versions satisfy the electrical characteristics shown in this manual, but actual electrical characteristic values, operating margins, noise margins, and other properties may vary due to differences in manufacturing process, on-chip ROM, layout patterns, and so on. When system evaluation testing is carried out using the flash memory version, the same evaluation testing should also be conducted for the mask ROM version when changing over to that version. Rev. 1.00 Dec. 13, 2007 Page 322 of 380 REJ09B0430-0100 Appendix Appendix A. A.1 Instruction Set Instruction List Condition Code Symbol Rd Rs Rn ERd ERs ERn (EAd) (EAs) PC SP CCR N Z V C disp + - x / Description General destination register General source register General register General destination register (address register or 32-bit register) General source register (address register or 32-bit register) General register (32-bit register) Destination operand Source operand Program counter Stack pointer Condition-code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Displacement Transfer from the operand on the left to the operand on the right, or transition from the state on the left to the state on the right Addition of the operands on both sides Subtraction of the operand on the right from the operand on the left Multiplication of the operands on both sides Division of the operand on the left by the operand on the right Logical AND of the operands on both sides Logical OR of the operands on both sides Logical exclusive OR of the operands on both sides Rev. 1.00 Dec. 13, 2007 Page 323 of 380 REJ09B0430-0100 Appendix Symbol ( ), < > Description NOT (logical complement) Contents of operand Note: General registers include 8-bit registers (R0H to R7H and R0L to R7L) and 16-bit registers (R0 to R7 and E0 to E7). Condition Code Notation (cont) Symbol Description Changed according to execution result Undetermined (no guaranteed value) Cleared to 0 Set to 1 Not affected by execution of the instruction Varies depending on conditions, described in notes * 0 1 -- Rev. 1.00 Dec. 13, 2007 Page 324 of 380 REJ09B0430-0100 Appendix Table A.1 Instruction Set 1. Data Transfer Instructions Addressing Mode and Instruction Length (bytes) @-ERn/@ERn+ Operand Size Condition Code No. of States*1 @(d, ERn) I H N Z V C MOV MOV.B #xx:8, Rd MOV.B Rs, Rd MOV.B @ERs, Rd MOV.B @(d:16, ERs), Rd MOV.B @(d:24, ERs), Rd MOV.B @ERs+, Rd B B B B B B 2 2 2 4 8 2 ---- ---- ---- ---- ---- ---- #xx:8 Rd8 Rs8 Rd8 @ERs Rd8 @(d:16, ERs) Rd8 @(d:24, ERs) Rd8 @ERs Rd8 ERs32+1 ERs32 2 4 6 2 4 8 2 @aa:8 Rd8 @aa:16 Rd8 @aa:24 Rd8 Rs8 @ERd Rs8 @(d:16, ERd) Rs8 @(d:24, ERd) ERd32-1 ERd32 Rs8 @ERd 2 4 6 Rs8 @aa:8 Rs8 @aa:16 Rs8 @aa:24 #xx:16 Rd16 2 2 4 8 2 Rs16 Rd16 @ERs Rd16 @(d:16, ERs) Rd16 @(d:24, ERs) Rd16 @ERs Rd16 ERs32+2 @ERd32 4 6 2 4 8 @aa:16 Rd16 @aa:24 Rd16 Rs16 @ERd Rs16 @(d:16, ERd) Rs16 @(d:24, ERd) 0-- 0-- 0-- 0-- 0-- 0-- 2 2 4 6 10 6 MOV.B @aa:8, Rd MOV.B @aa:16, Rd MOV.B @aa:24, Rd MOV.B Rs, @ERd MOV.B Rs, @(d:16, ERd) MOV.B Rs, @(d:24, ERd) MOV.B Rs, @-ERd B B B B B B B ---- ---- ---- ---- ---- ---- ---- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 4 6 8 4 6 10 6 MOV.B Rs, @aa:8 MOV.B Rs, @aa:16 MOV.B Rs, @aa:24 MOV.W #xx:16, Rd MOV.W Rs, Rd MOV.W @ERs, Rd B B B W4 W W ---- ---- ---- ---- ---- ---- ---- ---- ---- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 4 6 8 4 2 4 6 10 6 MOV.W @(d:16, ERs), Rd W MOV.W @(d:24, ERs), Rd W MOV.W @ERs+, Rd W MOV.W @aa:16, Rd MOV.W @aa:24, Rd MOV.W Rs, @ERd W W W ---- ---- ---- ---- ---- 0-- 0-- 0-- 0-- 0-- 6 8 4 6 10 MOV.W Rs, @(d:16, ERd) W MOV.W Rs, @(d:24, ERd) W Rev. 1.00 Dec. 13, 2007 Page 325 of 380 REJ09B0430-0100 Advanced Mnemonic Operation @(d, PC) Normal @@aa @ERn @aa #xx Rn -- Appendix Addressing Mode and Instruction Length (bytes) @-ERn/@ERn+ Operand Size Condition Code No. of States*1 @(d, ERn) I H N Z V C MOV MOV.W Rs, @-ERd MOV.W Rs, @aa:16 MOV.W Rs, @aa:24 MOV.L #xx:32, Rd MOV.L ERs, ERd MOV.L @ERs, ERd MOV.L @(d:16, ERs), ERd MOV.L @(d:24, ERs), ERd MOV.L @ERs+, ERd W 2 ERd32-2 ERd32 Rs16 @ERd 4 6 Rs16 @aa:16 Rs16 @aa:24 #xx:32 Rd32 ERs32 ERd32 ---- 0-- 6 W W L L L L L L 6 2 4 6 10 4 ---- ---- ---- ---- ---- ---- ---- ---- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 6 8 6 2 8 10 14 10 @ERs ERd32 @(d:16, ERs) ERd32 @(d:24, ERs) ERd32 @ERs ERd32 ERs32+4 ERs32 6 8 @aa:16 ERd32 @aa:24 ERd32 ERs32 @ERd 6 10 4 ERs32 @(d:16, ERd) ERs32 @(d:24, ERd) ERd32-4 ERd32 ERs32 @ERd 6 8 ERs32 @aa:16 ERs32 @aa:24 2 @SP Rn16 SP+2 SP 4 @SP ERn32 SP+4 SP 2 SP-2 SP Rn16 @SP 4 SP-4 SP ERn32 @SP 4 Cannot be used in this LSI Cannot be used in this LSI MOV.L @aa:16, ERd MOV.L @aa:24, ERd MOV.L ERs, @ERd MOV.L ERs, @(d:16, ERd) MOV.L ERs, @(d:24, ERd) MOV.L ERs, @-ERd L L L L L L 4 ---- ---- ---- ---- ---- ---- 0-- 0-- 0-- 0-- 0-- 0-- 10 12 8 10 14 10 MOV.L ERs, @aa:16 MOV.L ERs, @aa:24 POP POP.W Rn POP.L ERn L L W ---- ---- ---- 0-- 0-- 0-- 10 12 6 L ---- 0-- 10 PUSH PUSH.W Rn PUSH.L ERn W ---- 0-- 6 L ---- 0-- 10 MOVFPE MOVFPE @aa:16, Rd B Cannot be used in this LSI Cannot be used in this LSI MOVTPE MOVTPE Rs, @aa:16 B 4 Rev. 1.00 Dec. 13, 2007 Page 326 of 380 REJ09B0430-0100 Advanced Mnemonic Operation @(d, PC) Normal @@aa @ERn @aa #xx Rn -- Appendix 2. Arithmetic Instructions Addressing Mode and Instruction Length (bytes) @-ERn/@ERn+ Operand Size Condition Code No. of States*1 @(d, ERn) I H N Z V C ADD ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W #xx:16, Rd ADD.W Rs, Rd ADD.L #xx:32, ERd B B 2 2 -- -- Rd8+#xx:8 Rd8 Rd8+Rs8 Rd8 Rd16+#xx:16 Rd16 2 Rd16+Rs16 Rd16 ERd32+#xx:32 ERd32 2 ERd32+ERs32 ERd32 Rd8+#xx:8 +C Rd8 2 2 2 2 2 2 2 2 2 2 Rd8+Rs8 +C Rd8 ERd32+1 ERd32 ERd32+2 ERd32 ERd32+4 ERd32 Rd8+1 Rd8 Rd16+1 Rd16 Rd16+2 Rd16 ERd32+1 ERd32 ERd32+2 ERd32 Rd8 decimal adjust Rd8 Rd8-Rs8 Rd8 Rd16-#xx:16 Rd16 2 Rd16-Rs16 Rd16 2 2 4 2 6 W4 W L 6 -- (1) -- (1) -- (2) ADD.L ERs, ERd L -- (2) 2 ADDX ADDX.B #xx:8, Rd ADDX.B Rs, Rd ADDS ADDS.L #1, ERd ADDS.L #2, ERd ADDS.L #4, ERd INC INC.B Rd INC.W #1, Rd INC.W #2, Rd INC.L #1, ERd INC.L #2, ERd DAA SUB DAA Rd B B L L L B W W L L B 2 -- -- (3) (3) 2 2 2 2 2 2 2 2 2 2 2 ------------ ------------ ------------ ---- ---- ---- ---- ---- --* -- -- -- -- -- *-- SUB.B Rs, Rd SUB.W #xx:16, Rd SUB.W Rs, Rd SUB.L #xx:32, ERd SUB.L ERs, ERd B W4 W L L B B L L L B W W 2 6 2 -- 2 4 2 6 2 2 2 2 2 2 2 2 2 -- (1) -- (1) ERd32-#xx:32 ERd32 -- (2) 2 ERd32-ERs32 ERd32 -- (2) SUBX SUBX.B #xx:8, Rd SUBX.B Rs, Rd SUBS SUBS.L #1, ERd SUBS.L #2, ERd SUBS.L #4, ERd DEC DEC.B Rd DEC.W #1, Rd DEC.W #2, Rd Rd8-#xx:8-C Rd8 2 2 2 2 2 2 2 Rd8-Rs8-C Rd8 ERd32-1 ERd32 ERd32-2 ERd32 ERd32-4 ERd32 Rd8-1 Rd8 Rd16-1 Rd16 Rd16-2 Rd16 -- -- (3) (3) ------------ ------------ ------------ ---- ---- ---- -- -- -- Rev. 1.00 Dec. 13, 2007 Page 327 of 380 REJ09B0430-0100 Advanced Mnemonic Operation @(d, PC) Normal @@aa @ERn @aa #xx Rn -- Appendix Addressing Mode and Instruction Length (bytes) @-ERn/@ERn+ Operand Size Condition Code No. of States*1 @(d, ERn) I H N Z V C DEC DEC.L #1, ERd DEC.L #2, ERd DAS DAS.Rd L L B 2 2 2 ---- ---- --* ERd32-1 ERd32 ERd32-2 ERd32 Rd8 decimal adjust Rd8 Rd8 x Rs8 Rd16 (unsigned multiplication) Rd16 x Rs16 ERd32 (unsigned multiplication) Rd8 x Rs8 Rd16 (signed multiplication) Rd16 x Rs16 ERd32 (signed multiplication) Rd16 / Rs8 Rd16 (RdH: remainder, RdL: quotient) (unsigned division) ERd32 / Rs16 ERd32 (Ed: remainder, Rd: quotient) (unsigned division) Rd16 / Rs8 Rd16 (RdH: remainder, RdL: quotient) (signed division) ERd32 / Rs16 ERd32 (Ed: remainder, Rd: quotient) (signed division) Rd8-#xx:8 -- -- 2 2 2 *-- MULXU MULXU. B Rs, Rd B 2 ------------ 14 MULXU. W Rs, ERd W 2 ------------ 22 MULXS MULXS. B Rs, Rd B 4 ---- ---- 16 MULXS. W Rs, ERd W 4 ---- ---- 24 DIVXU DIVXU. B Rs, Rd B 2 -- -- (6) (7) -- -- 14 DIVXU. W Rs, ERd W 2 -- -- (6) (7) -- -- 22 DIVXS DIVXS. B Rs, Rd B 4 -- -- (8) (7) -- -- 16 DIVXS. W Rs, ERd W 4 -- -- (8) (7) -- -- 24 CMP CMP.B #xx:8, Rd CMP.B Rs, Rd CMP.W #xx:16, Rd CMP.W Rs, Rd CMP.L #xx:32, ERd CMP.L ERs, ERd B B 2 2 -- -- 2 2 4 2 4 2 Rd8-Rs8 Rd16-#xx:16 W4 W L L 6 2 2 -- (1) -- (1) -- (2) -- (2) Rd16-Rs16 ERd32-#xx:32 ERd32-ERs32 Rev. 1.00 Dec. 13, 2007 Page 328 of 380 REJ09B0430-0100 Advanced Mnemonic Operation @(d, PC) Normal @@aa @ERn @aa #xx Rn -- Appendix Addressing Mode and Instruction Length (bytes) No. of States*1 Condition Code @(d, ERn) I H N Z V C NEG NEG.B Rd NEG.W Rd NEG.L ERd EXTU EXTU.W Rd EXTU.L ERd B W L W 2 2 2 2 -- -- -- 0-Rd8 Rd8 0-Rd16 Rd16 0-ERd32 ERd32 0 ( 2 2 2 2 ---- 0 0-- L 2 ---- 0 0-- 2 EXTS EXTS.W Rd EXTS.L ERd W 2 ---- 0-- 2 L 2 ---- 0-- 2 Rev. 1.00 Dec. 13, 2007 Page 329 of 380 REJ09B0430-0100 Advanced Mnemonic @-ERn/@ERn+ Operand Size Operation @(d, PC) Normal @@aa @ERn @aa #xx Rn -- Appendix 3. Logic Instructions Addressing Mode and Instruction Length (bytes) No. of States*1 Condition Code @(d, ERn) I H N Z V C AND AND.B #xx:8, Rd AND.B Rs, Rd AND.W #xx:16, Rd AND.W Rs, Rd AND.L #xx:32, ERd AND.L ERs, ERd B B 2 2 ---- ---- ---- ---- Rd8#xx:8 Rd8 Rd8Rs8 Rd8 Rd16#xx:16 Rd16 2 Rd16Rs16 Rd16 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 2 2 4 2 6 4 2 2 4 2 6 4 2 2 4 2 6 4 2 2 2 W4 W L L B B W4 W L L B B W4 W L L B W L 6 4 2 2 2 2 2 2 6 4 2 2 2 6 4 ERd32#xx:32 ERd32 -- -- ERd32ERs32 ERd32 -- -- Rd8#xx:8 Rd8 Rd8Rs8 Rd8 Rd16#xx:16 Rd16 Rd16Rs16 Rd16 ---- ---- ---- ---- OR OR.B #xx:8, Rd OR.B Rs, Rd OR.W #xx:16, Rd OR.W Rs, Rd OR.L #xx:32, ERd OR.L ERs, ERd ERd32#xx:32 ERd32 -- -- ERd32ERs32 ERd32 -- -- Rd8#xx:8 Rd8 Rd8Rs8 Rd8 Rd16#xx:16 Rd16 Rd16Rs16 Rd16 ---- ---- ---- ---- XOR XOR.B #xx:8, Rd XOR.B Rs, Rd XOR.W #xx:16, Rd XOR.W Rs, Rd XOR.L #xx:32, ERd XOR.L ERs, ERd ERd32#xx:32 ERd32 -- -- ERd32ERs32 ERd32 -- -- Rd8 Rd8 Rd16 Rd16 Rd32 Rd32 ---- ---- ---- NOT NOT.B Rd NOT.W Rd NOT.L ERd Rev. 1.00 Dec. 13, 2007 Page 330 of 380 REJ09B0430-0100 Advanced Mnemonic @-ERn/@ERn+ Operand Size Operation @(d, PC) Normal @@aa @ERn @aa #xx Rn -- Appendix 4. Shift Instructions Addressing Mode and Instruction Length (bytes) @-ERn/@ERn+ Operand Size Condition Code No. of States*1 @(d, ERn) I H N Z V C SHAL SHAL.B Rd SHAL.W Rd SHAL.L ERd SHAR SHAR.B Rd SHAR.W Rd SHAR.L ERd SHLL SHLL.B Rd SHLL.W Rd SHLL.L ERd SHLR SHLR.B Rd SHLR.W Rd SHLR.L ERd ROTXL ROTXL.B Rd B W L B W L B W L B W L B W L B W L B W L B W L 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 C MSB LSB C MSB C MSB 0 MSB C MSB LSB C MSB C MSB LSB LSB LSB LSB LSB 0 ---- ---- ---- ---- ---- ---- ---- 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ---- ---- ---- C ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ROTXL.W Rd ROTXL.L ERd ROTXR ROTXR.B Rd ROTXR.W Rd ROTXR.L ERd ROTL ROTL.B Rd ROTL.W Rd ROTL.L ERd ROTR ROTR.B Rd ROTR.W Rd ROTR.L ERd C MSB LSB ---- ---- Rev. 1.00 Dec. 13, 2007 Page 331 of 380 REJ09B0430-0100 Advanced Mnemonic Operation @(d, PC) Normal @@aa @ERn @aa #xx Rn -- Appendix 5. Bit-Manipulation Instructions Addressing Mode and Instruction Length (bytes) No. of States*1 Condition Code @(d, ERn) I H N Z V C BSET BSET #xx:3, Rd BSET #xx:3, @ERd BSET #xx:3, @aa:8 BSET Rn, Rd BSET Rn, @ERd BSET Rn, @aa:8 BCLR BCLR #xx:3, Rd BCLR #xx:3, @ERd BCLR #xx:3, @aa:8 BCLR Rn, Rd BCLR Rn, @ERd BCLR Rn, @aa:8 BNOT BNOT #xx:3, Rd B B B B B B B B B B B B B 2 4 4 2 4 4 2 4 4 2 4 4 2 (#xx:3 of Rd8) 1 (#xx:3 of @ERd) 1 (#xx:3 of @aa:8) 1 (Rn8 of Rd8) 1 (Rn8 of @ERd) 1 (Rn8 of @aa:8) 1 (#xx:3 of Rd8) 0 (#xx:3 of @ERd) 0 (#xx:3 of @aa:8) 0 (Rn8 of Rd8) 0 (Rn8 of @ERd) 0 (Rn8 of @aa:8) 0 (#xx:3 of Rd8) (#xx:3 of Rd8) 4 (#xx:3 of @ERd) (#xx:3 of @ERd) 4 (#xx:3 of @aa:8) (#xx:3 of @aa:8) (Rn8 of Rd8) (Rn8 of Rd8) 4 (Rn8 of @ERd) (Rn8 of @ERd) 4 (Rn8 of @aa:8) (Rn8 of @aa:8) (#xx:3 of Rd8) Z 4 4 (#xx:3 of @ERd) Z (#xx:3 of @aa:8) Z (Rn8 of @Rd8) Z 4 4 (Rn8 of @ERd) Z (Rn8 of @aa:8) Z (#xx:3 of Rd8) C ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ 2 8 8 2 8 8 2 8 8 2 8 8 2 BNOT #xx:3, @ERd B ------------ 8 BNOT #xx:3, @aa:8 B ------------ 8 BNOT Rn, Rd B 2 ------------ 2 BNOT Rn, @ERd B ------------ 8 BNOT Rn, @aa:8 B ------------ 8 BTST BTST #xx:3, Rd BTST #xx:3, @ERd BTST #xx:3, @aa:8 BTST Rn, Rd BTST Rn, @ERd BTST Rn, @aa:8 BLD BLD #xx:3, Rd B B B B B B B 2 ------ ------ ------ ------ ------ ------ ---- ---- ---- ---- ---- ---- 2 6 6 2 6 6 2 2 2 ---------- Rev. 1.00 Dec. 13, 2007 Page 332 of 380 REJ09B0430-0100 Advanced Mnemonic @-ERn/@ERn+ Operand Size Operation @(d, PC) Normal @@aa @ERn @aa #xx Rn -- Appendix Addressing Mode and Instruction Length (bytes) @-ERn/@ERn+ Operand Size Condition Code No. of States*1 @(d, ERn) I H N Z V C BLD BLD #xx:3, @ERd BLD #xx:3, @aa:8 B B B B B B B B B B B B B B B B B B B B B B B B B B B B B 2 2 2 2 2 2 2 2 2 4 4 ---------- ---------- ---------- ---------- ---------- (#xx:3 of @ERd) C (#xx:3 of @aa:8) C (#xx:3 of Rd8) C (#xx:3 of @ERd) C 4 (#xx:3 of @aa:8) C C (#xx:3 of Rd8) C (#xx:3 of @ERd24) 4 C (#xx:3 of @aa:8) C (#xx:3 of Rd8) C (#xx:3 of @ERd24) 4 C (#xx:3 of @aa:8) C(#xx:3 of Rd8) C C(#xx:3 of @ERd24) C 4 C(#xx:3 of @aa:8) C C (#xx:3 of Rd8) C 6 6 2 6 6 2 8 8 2 8 8 2 6 6 2 6 6 2 6 6 2 6 6 2 6 6 2 6 6 BILD BILD #xx:3, Rd BILD #xx:3, @ERd BILD #xx:3, @aa:8 BST BST #xx:3, Rd BST #xx:3, @ERd BST #xx:3, @aa:8 BIST BIST #xx:3, Rd BIST #xx:3, @ERd BIST #xx:3, @aa:8 BAND BAND #xx:3, Rd BAND #xx:3, @ERd BAND #xx:3, @aa:8 BIAND BIAND #xx:3, Rd BIAND #xx:3, @ERd BIAND #xx:3, @aa:8 BOR BOR #xx:3, Rd BOR #xx:3, @ERd BOR #xx:3, @aa:8 BIOR BIOR #xx:3, Rd BIOR #xx:3, @ERd BIOR #xx:3, @aa:8 BXOR BXOR #xx:3, Rd BXOR #xx:3, @ERd BXOR #xx:3, @aa:8 BIXOR BIXOR #xx:3, Rd BIXOR #xx:3, @ERd BIXOR #xx:3, @aa:8 4 ------------ ------------ ------------ ------------ ------------ ------------ ---------- ---------- ---------- ---------- 4 4 4 4 4 C (#xx:3 of @ERd24) C -- -- -- -- -- C (#xx:3 of @aa:8) C C(#xx:3 of Rd8) C C(#xx:3 of @ERd24) C 4 C(#xx:3 of @aa:8) C C (#xx:3 of Rd8) C ---------- ---------- ---------- ---------- ---------- 4 4 4 C (#xx:3 of @ERd24) C -- -- -- -- -- C (#xx:3 of @aa:8) C C(#xx:3 of Rd8) C C(#xx:3 of @ERd24) C 4 C(#xx:3 of @aa:8) C C (#xx:3 of Rd8) C ---------- ---------- ---------- ---------- ---------- 4 4 4 C (#xx:3 of @ERd24) C -- -- -- -- -- C (#xx:3 of @aa:8) C ---------- Rev. 1.00 Dec. 13, 2007 Page 333 of 380 REJ09B0430-0100 Advanced Mnemonic Operation @(d, PC) Normal @@aa @ERn @aa #xx Rn -- Appendix 6. Branching Instructions Addressing Mode and Instruction Length (bytes) No. of States*1 Condition Code @(d, ERn) Branch Condition If condition Always is true then PC PC+d Never else next; C Z = 0 I H N Z V C Bcc BRA d:8 (BT d:8) BRA d:16 (BT d:16) BRN d:8 (BF d:8) BRN d:16 (BF d:16) BHI d:8 BHI d:16 BLS d:8 BLS d:16 BCC d:8 (BHS d:8) BCC d:16 (BHS d:16) BCS d:8 (BLO d:8) BCS d:16 (BLO d:16) BNE d:8 BNE d:16 BEQ d:8 BEQ d:16 BVC d:8 BVC d:16 BVS d:8 BVS d:16 BPL d:8 BPL d:16 BMI d:8 BMI d:16 BGE d:8 BGE d:16 BLT d:8 BLT d:16 BGT d:8 BGT d:16 BLE d:8 BLE d:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 ------------ ------------ ------------ ------------ ------------ ------------ 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 C Z = 1 ------------ ------------ C=0 ------------ ------------ C=1 ------------ ------------ Z=0 ------------ ------------ Z=1 ------------ ------------ V=0 ------------ ------------ V=1 ------------ ------------ N=0 ------------ ------------ N=1 ------------ ------------ NV = 0 ------------ ------------ NV = 1 ------------ ------------ Z (NV) = 0 -- -- -- -- -- -- ------------ Z (NV) = 1 -- -- -- -- -- -- ------------ Rev. 1.00 Dec. 13, 2007 Page 334 of 380 REJ09B0430-0100 Advanced Mnemonic @-ERn/@ERn+ Operand Size Operation @(d, PC) Normal @@aa @ERn @aa #xx Rn -- Appendix Addressing Mode and Instruction Length (bytes) No. of States*1 Condition Code @(d, ERn) I H N Z V C JMP JMP @ERn JMP @aa:24 JMP @@aa:8 -- -- -- -- 2 4 2 2 PC ERn PC aa:24 PC @aa:8 PC @-SP PC PC+d:8 PC @-SP PC PC+d:16 PC @-SP PC ERn 4 PC @-SP PC aa:24 2 PC @-SP PC @aa:8 2 PC @SP+ ------------ ------------ ------------ ------------ 8 6 4 6 10 8 BSR BSR d:8 BSR d:16 JSR -- 4 ------------ 8 10 JSR @ERn -- 2 ------------ 6 JSR @aa:24 -- ------------ 8 10 JSR @@aa:8 -- ------------ 8 12 RTS RTS -- ------------ 8 10 Rev. 1.00 Dec. 13, 2007 Page 335 of 380 REJ09B0430-0100 Advanced 8 Mnemonic @-ERn/@ERn+ Operand Size Operation @(d, PC) Normal @@aa @ERn @aa #xx Rn -- Appendix 7. System Control Instructions Addressing Mode and Instruction Length (bytes) No. of States*1 Condition Code @(d, ERn) I H N Z V C RTE RTE -- CCR @SP+ PC @SP+ Transition to powerdown state 10 SLEEP SLEEP -- 2 2 4 6 10 4 2 LDC LDC #xx:8, CCR LDC Rs, CCR LDC @ERs, CCR LDC @(d:16, ERs), CCR LDC @(d:24, ERs), CCR LDC @ERs+, CCR B B W W W W #xx:8 CCR Rs8 CCR @ERs CCR @(d:16, ERs) CCR @(d:24, ERs) CCR @ERs CCR ERs32+2 ERs32 6 8 2 4 6 10 4 @aa:16 CCR @aa:24 CCR CCR Rd8 CCR @ERd CCR @(d:16, ERd) CCR @(d:24, ERd) ERd32-2 ERd32 CCR @ERd 6 8 CCR @aa:16 CCR @aa:24 2 2 6 8 12 8 LDC @aa:16, CCR LDC @aa:24, CCR STC STC CCR, Rd STC CCR, @ERd STC CCR, @(d:16, ERd) STC CCR, @(d:24, ERd) STC CCR, @-ERd W W B W W W W 8 10 2 6 8 12 8 STC CCR, @aa:16 STC CCR, @aa:24 ANDC ANDC #xx:8, CCR ORC NOP ORC #xx:8, CCR XORC XORC #xx:8, CCR NOP W W B B B -- 2 2 2 8 10 CCR#xx:8 CCR CCR#xx:8 CCR CCR#xx:8 CCR 2 PC PC+2 2 2 2 2 Rev. 1.00 Dec. 13, 2007 Page 336 of 380 REJ09B0430-0100 Advanced Mnemonic @-ERn/@ERn+ Operand Size Operation @(d, PC) Normal @@aa @ERn @aa #xx Rn -- Appendix 8. Block Transfer Instructions Addressing Mode and Instruction Length (bytes) No. of States*1 Condition Code @(d, ERn) I H N Z V C EEPMOV EEPMOV. B -- 4 if R4L 0 then repeat @R5 @R6 R5+1 R5 R6+1 R6 R4L-1 R4L until R4L=0 else next 4 if R4 0 then repeat @R5 @R6 R5+1 R5 R6+1 R6 R4-1 R4 until R4=0 else next -- -- -- -- -- -- 8+ 4n*2 EEPMOV. W -- -- -- -- -- -- -- 8+ 4n*2 Notes: 1. The number of states in cases where the instruction code and its operands are located in on-chip memory is shown here. For other cases, see appendix A.3, Number of Execution States. 2. n is the value set in register R4L or R4. (1) (2) (3) (4) (5) Set to 1 when a carry or borrow occurs at bit 11; otherwise cleared to 0. Set to 1 when a carry or borrow occurs at bit 27; otherwise cleared to 0. Retains its previous value when the result is zero; otherwise cleared to 0. Set to 1 when the adjustment produces a carry; otherwise retains its previous value. The number of states required for execution of an instruction that transfers data in synchronization with the E clock is variable. (6) Set to 1 when the divisor is negative; otherwise cleared to 0. (7) Set to 1 when the divisor is zero; otherwise cleared to 0. (8) Set to 1 when the quotient is negative; otherwise cleared to 0. Rev. 1.00 Dec. 13, 2007 Page 337 of 380 REJ09B0430-0100 Advanced Mnemonic @-ERn/@ERn+ Operand Size Operation @(d, PC) Normal @@aa @ERn @aa #xx Rn -- A.2 Appendix Table A.2 Instruction code: Instruction when most significant bit of BH is 1. 4 ORC ADD SUB Table A-2 Table A-2 (2) (2) CMP SUBX MOV OR.B XOR.B AND.B Table A-2 (2) XORC ANDC LDC Table A-2 Table A-2 (2) (2) ADDX 5 6 7 8 9 A B C D E F Table A-2 (2) Table A-2 (2) REJ09B0430-0100 1st byte 2nd byte AH AL BH BL Instruction when most significant bit of BH is 0. 3 LDC AL AH 0 1 2 0 NOP Table A-2 (2) STC Operation Code Map 1 Table A-2 Table A-2 Table A-2 Table A-2 (2) (2) (2) (2) 2 MOV.B Rev. 1.00 Dec. 13, 2007 Page 338 of 380 Operation Code Map (1) 3 BLS BVS JMP MOV MOV BIOR ADD ADDX CMP SUBX OR XOR AND MOV BIXOR BIAND BILD Table A-2 Table A-2 EEPMOV (2) (2) Table A-2 (3) DIVXU BST OR BTST BOR BXOR BAND BIST BLD XOR AND RTS BSR RTE TRAPA Table A-2 (2) BCC BCS BNE BEQ BVC BPL BMI BGE BSR BLT BGT JSR BLE 4 BRA BRN BHI 5 MULXU DIVXU MULXU 6 BSET BNOT BCLR 7 8 9 A B C D E F Table A.2 Instruction code: 1st byte 2nd byte AH AL BH BL 3 LDC/STC ADD INC ADDS MOV SHLL SHAL SHAR ROTL ROTR EXTU EXTU NEG SHLR ROTXL ROTXR NOT SHAL SHAR ROTL ROTR NEG SUB DEC DEC SUB CMP BLS BCC OR OR XOR XOR SUB SUB BCS BNE AND AND BEQ BVC BVS BPL BMI BGE BLT BGT BLE DEC DEC EXTS EXTS INC INC INC SLEEP Table A-2 Table A-2 (3) (3) 4 5 6 7 8 9 A B C D E F Table A-2 (3) BH AH AL 0 1 2 01 MOV 0A INC 0B ADDS Operation Code Map (2) 0F DAA 10 SHLL 11 SHLR 12 ROTXL 13 ROTXR 17 NOT 1A DEC 1B SUBS 1F DAS 58 BRA BRN BHI 79 MOV ADD CMP Rev. 1.00 Dec. 13, 2007 Page 339 of 380 REJ09B0430-0100 7A MOV ADD CMP Appendix Appendix Table A.2 Instruction code: Instruction when most significant bit of DH is 1. REJ09B0430-0100 1st byte 2nd byte 3rd byte 4th byte AH AL BH BL CH CL DH DL Instruction when most significant bit of DH is 0. CL 3 4 5 6 7 8 9 A B C D E F AH ALBH BLCH LDC STC STC LDC LDC STC 0 1 2 01406 LDC STC Rev. 1.00 Dec. 13, 2007 Page 340 of 380 Operation Code Map (3) 01C05 DIVXS OR AND BTST BOR BTST BIOR BIST BIXOR BIAND BILD BST BXOR BAND BLD XOR MULXS MULXS 01D05 DIVXS 01F06 7Cr06 * 1 7Cr07 * 1 7Dr06 * 1 BSET BNOT BCLR 7Dr07 * 1 BTST BOR BTST BIOR BIXOR BIAND BILD BST BIST BXOR BAND BLD BSET BNOT BCLR 7Eaa6 * 2 7Eaa7 * 2 7Faa6 * 2 BSET BNOT BCLR 7Faa7 * 2 BSET BNOT BCLR Notes: 1. r is the register designation field. 2. aa is the absolute address field. Appendix A.3 Number of Execution States The status of execution for each instruction of the H8/300H CPU and the method of calculating the number of states required for instruction execution are shown below. Table A.4 shows the number of cycles of each type occurring in each instruction, such as instruction fetch and data read/write. Table A.3 shows the number of states required for each cycle. The total number of states required for execution of an instruction can be calculated by the following expression: Execution states = I x SI + J x SJ + K x SK + L x SL + M x SM + N x SN Examples: When instruction is fetched from on-chip ROM, and an on-chip RAM is accessed. BSET #0, @FF00 From table A.4: I = L = 2, J = K = M = N= 0 From table A.3: SI = 2, SL = 2 Number of states required for execution = 2 x 2 + 2 x 2 = 8 When instruction is fetched from on-chip ROM, branch address is read from on-chip ROM, and on-chip RAM is used for stack area. JSR @@ 30 From table A.4: I = 2, J = K = 1, From table A.3: SI = SJ = SK = 2 Number of states required for execution = 2 x 2 + 1 x 2+ 1 x 2 = 8 L=M=N=0 Rev. 1.00 Dec. 13, 2007 Page 341 of 380 REJ09B0430-0100 Appendix Table A.3 Number of Cycles in Each Instruction Access Location On-Chip Memory SI SJ SK SL SM SN 2 or 3* -- 1 2 On-Chip Peripheral Module -- Execution Status (Instruction Cycle) Instruction fetch Branch address read Stack operation Byte data access Word data access Internal operation Note: * Depends on which on-chip peripheral module is accessed. See section 13.1, Register Addresses (Address Order). Rev. 1.00 Dec. 13, 2007 Page 342 of 380 REJ09B0430-0100 Appendix Table A.4 Number of Cycles in Each Instruction Instruction Fetch I 1 1 2 1 3 1 1 1 1 1 1 2 1 3 2 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 Stack Branch Addr. Read Operation K J Byte Data Access L Word Data Access M Internal Operation N Instruction Mnemonic ADD ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W #xx:16, Rd ADD.W Rs, Rd ADD.L #xx:32, ERd ADD.L ERs, ERd ADDS ADDX ADDS #1/2/4, ERd ADDX #xx:8, Rd ADDX Rs, Rd AND AND.B #xx:8, Rd AND.B Rs, Rd AND.W #xx:16, Rd AND.W Rs, Rd AND.L #xx:32, ERd AND.L ERs, ERd ANDC BAND ANDC #xx:8, CCR BAND #xx:3, Rd BAND #xx:3, @ERd BAND #xx:3, @aa:8 Bcc BRA d:8 (BT d:8) BRN d:8 (BF d:8) BHI d:8 BLS d:8 BCC d:8 (BHS d:8) BCS d:8 (BLO d:8) BNE d:8 BEQ d:8 BVC d:8 BVS d:8 BPL d:8 BMI d:8 BGE d:8 Rev. 1.00 Dec. 13, 2007 Page 343 of 380 REJ09B0430-0100 Appendix Instruction Fetch I 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Branch Stack Addr. Read Operation J K Byte Data Access L Word Data Access M Internal Operation N Instruction Mnemonic Bcc BLT d:8 BGT d:8 BLE d:8 BRA d:16(BT d:16) BRN d:16(BF d:16) BHI d:16 BLS d:16 BCC d:16(BHS d:16) BCS d:16(BLO d:16) BNE d:16 BEQ d:16 BVC d:16 BVS d:16 BPL d:16 BMI d:16 BGE d:16 BLT d:16 BGT d:16 BLE d:16 BCLR BCLR #xx:3, Rd BCLR #xx:3, @ERd BCLR #xx:3, @aa:8 BCLR Rn, Rd BCLR Rn, @ERd BCLR Rn, @aa:8 BIAND BIAND #xx:3, Rd BIAND #xx:3, @ERd BIAND #xx:3, @aa:8 BILD BILD #xx:3, Rd BILD #xx:3, @ERd BILD #xx:3, @aa:8 Rev. 1.00 Dec. 13, 2007 Page 344 of 380 REJ09B0430-0100 Appendix Instruction Fetch I 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 2 2 1 2 2 2 2 1 1 2 2 2 2 2 1 1 2 2 2 2 1 1 1 1 2 2 1 1 Branch Stack Addr. Read Operation J K Byte Data Access L Word Data Access M Internal Operation N Instruction Mnemonic BIOR BIOR #xx:3, Rd BIOR #xx:3, @ERd BIOR #xx:3, @aa:8 BIST BIST #xx:3, Rd BIST #xx:3, @ERd BIST #xx:3, @aa:8 BIXOR BIXOR #xx:3, Rd BIXOR #xx:3, @ERd BIXOR #xx:3, @aa:8 BLD BLD #xx:3, Rd BLD #xx:3, @ERd BLD #xx:3, @aa:8 BNOT BNOT #xx:3, Rd BNOT #xx:3, @ERd BNOT #xx:3, @aa:8 BNOT Rn, Rd BNOT Rn, @ERd BNOT Rn, @aa:8 BOR BOR #xx:3, Rd BOR #xx:3, @ERd BOR #xx:3, @aa:8 BSET BSET #xx:3, Rd BSET #xx:3, @ERd BSET #xx:3, @aa:8 BSET Rn, Rd BSET Rn, @ERd BSET Rn, @aa:8 BSR BSR d:8 BSR d:16 BST BST #xx:3, Rd BST #xx:3, @ERd BST #xx:3, @aa:8 Rev. 1.00 Dec. 13, 2007 Page 345 of 380 REJ09B0430-0100 Appendix Instruction Fetch I 1 2 2 1 2 2 1 2 2 1 1 2 1 3 1 1 1 1 1 1 2 2 1 1 2 2 1 1 1 1 2n+2*1 2n+2*1 12 20 12 20 1 1 1 1 1 1 Branch Stack Addr. Read Operation J K Byte Data Access L Word Data Access M Internal Operation N Instruction Mnemonic BTST BTST #xx:3, Rd BTST #xx:3, @ERd BTST #xx:3, @aa:8 BTST Rn, Rd BTST Rn, @ERd BTST Rn, @aa:8 BXOR BXOR #xx:3, Rd BXOR #xx:3, @ERd BXOR #xx:3, @aa:8 CMP CMP.B #xx:8, Rd CMP.B Rs, Rd CMP.W #xx:16, Rd CMP.W Rs, Rd CMP.L #xx:32, ERd CMP.L ERs, ERd DAA DAS DEC DAA Rd DAS Rd DEC.B Rd DEC.W #1/2, Rd DEC.L #1/2, ERd DUVXS DIVXS.B Rs, Rd DIVXS.W Rs, ERd DIVXU DIVXU.B Rs, Rd DIVXU.W Rs, ERd EEPMOV EEPMOV.B EEPMOV.W EXTS EXTS.W Rd EXTS.L ERd EXTU EXTU.W Rd EXTU.L ERd Rev. 1.00 Dec. 13, 2007 Page 346 of 380 REJ09B0430-0100 Appendix Instruction Fetch I 1 1 1 2 2 2 2 2 2 1 1 2 3 5 2 3 4 1 1 1 2 4 1 1 2 3 1 2 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 2 1 1 1 1 1 2 2 2 Branch Stack Addr. Read Operation J K Byte Data Access L Word Data Access M Internal Operation N Instruction Mnemonic INC INC.B Rd INC.W #1/2, Rd INC.L #1/2, ERd JMP JMP @ERn JMP @aa:24 JMP @@aa:8 JSR JSR @ERn JSR @aa:24 JSR @@aa:8 LDC LDC #xx:8, CCR LDC Rs, CCR LDC@ERs, CCR LDC@(d:16, ERs), CCR LDC@(d:24,ERs), CCR LDC@ERs+, CCR LDC@aa:16, CCR LDC@aa:24, CCR MOV MOV.B #xx:8, Rd MOV.B Rs, Rd MOV.B @ERs, Rd MOV.B @(d:16, ERs), Rd MOV.B @(d:24, ERs), Rd MOV.B @ERs+, Rd MOV.B @aa:8, Rd MOV.B @aa:16, Rd MOV.B @aa:24, Rd MOV.B Rs, @Erd MOV.B Rs, @(d:16, ERd) MOV.B Rs, @(d:24, ERd) MOV.B Rs, @-ERd MOV.B Rs, @aa:8 Rev. 1.00 Dec. 13, 2007 Page 347 of 380 REJ09B0430-0100 Appendix Instruction Fetch I 2 3 2 1 1 2 4 1 2 3 1 2 4 1 2 3 3 1 2 3 5 2 3 4 2 3 5 2 3 4 2 Instruction Mnemonic MOV MOV.B Rs, @aa:16 MOV.B Rs, @aa:24 MOV.W #xx:16, Rd MOV.W Rs, Rd MOV.W @ERs, Rd MOV.W @(d:16,ERs), Rd MOV.W @(d:24,ERs), Rd MOV.W @ERs+, Rd MOV.W @aa:16, Rd MOV.W @aa:24, Rd MOV.W Rs, @ERd MOV.W Rs, @(d:16,ERd) MOV.W Rs, @(d:24,ERd) MOV MOV.W Rs, @-ERd MOV.W Rs, @aa:16 MOV.W Rs, @aa:24 MOV.L #xx:32, ERd MOV.L ERs, ERd MOV.L @ERs, ERd MOV.L @(d:16,ERs), ERd MOV.L @(d:24,ERs), ERd MOV.L @ERs+, ERd MOV.L @aa:16, ERd MOV.L @aa:24, ERd MOV.L ERs,@ERd MOV.L ERs, @(d:16,ERd) MOV.L ERs, @(d:24,ERd) MOV.L ERs, @-ERd MOV.L ERs, @aa:16 MOV.L ERs, @aa:24 MOVFPE MOVTPE MOVFPE @aa:16, Rd* MOVTPE Rs,@aa:16*2 Branch Stack Addr. Read Operation J K Byte Data Access L 1 1 Word Data Access M Internal Operation N 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 2 2 2 2 Rev. 1.00 Dec. 13, 2007 Page 348 of 380 REJ09B0430-0100 Appendix Instruction Fetch I 2 2 1 1 1 1 1 1 1 1 1 1 1 2 1 3 2 1 1 2 1 2 1 1 1 1 1 1 1 1 1 1 2 1 2 2 2 2 2 Branch Stack Addr. Read Operation J K Byte Data Access L Word Data Access M Internal Operation N 12 20 12 20 Instruction Mnemonic MULXS MULXS.B Rs, Rd MULXS.W Rs, ERd MULXU MULXU.B Rs, Rd MULXU.W Rs, ERd NEG NEG.B Rd NEG.W Rd NEG.L ERd NOP NOT NOP NOT.B Rd NOT.W Rd NOT.L ERd OR OR.B #xx:8, Rd OR.B Rs, Rd OR.W #xx:16, Rd OR.W Rs, Rd OR.L #xx:32, ERd OR.L ERs, ERd ORC POP ORC #xx:8, CCR POP.W Rn POP.L ERn PUSH PUSH.W Rn PUSH.L ERn ROTL ROTL.B Rd ROTL.W Rd ROTL.L ERd ROTR ROTR.B Rd ROTR.W Rd ROTR.L ERd ROTXL ROTXL.B Rd ROTXL.W Rd ROTXL.L ERd Rev. 1.00 Dec. 13, 2007 Page 349 of 380 REJ09B0430-0100 Appendix Instruction Fetch I 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 3 5 2 3 4 1 2 1 3 1 1 1 1 1 1 1 1 2 2 1 2 2 Branch Stack Addr. Read Operation J K Byte Data Access L Word Data Access M Internal Operation N Instruction Mnemonic ROTXR ROTXR.B Rd ROTXR.W Rd ROTXR.L ERd RTE RTS SHAL RTE RTS SHAL.B Rd SHAL.W Rd SHAL.L ERd SHAR SHAR.B Rd SHAR.W Rd SHAR.L ERd SHLL SHLL.B Rd SHLL.W Rd SHLL.L ERd SHLR SHLR.B Rd SHLR.W Rd SHLR.L ERd SLEEP STC SLEEP STC CCR, Rd STC CCR, @ERd STC CCR, @(d:16,ERd) STC CCR, @(d:24,ERd) STC CCR,@-ERd STC CCR, @aa:16 STC CCR, @aa:24 SUB SUB.B Rs, Rd SUB.W #xx:16, Rd SUB.W Rs, Rd SUB.L #xx:32, ERd SUB.L ERs, ERd SUBS SUBS #1/2/4, ERd Rev. 1.00 Dec. 13, 2007 Page 350 of 380 REJ09B0430-0100 Appendix Instruction Fetch I 1 1 1 1 2 1 3 2 1 Branch Stack Addr. Read Operation J K Byte Data Access L Word Data Access M Internal Operation N Instruction Mnemonic SUBX SUBX #xx:8, Rd SUBX. Rs, Rd XOR XOR.B #xx:8, Rd XOR.B Rs, Rd XOR.W #xx:16, Rd XOR.W Rs, Rd XOR.L #xx:32, ERd XOR.L ERs, ERd XORC XORC #xx:8, CCR Notes: 1. n: Specified value in R4L. The source and destination operands are accessed n+1 times respectively. 2. It cannot be used in this LSI. Rev. 1.00 Dec. 13, 2007 Page 351 of 380 REJ09B0430-0100 Appendix A.4 Combinations of Instructions and Addressing Modes Combinations of Instructions and Addressing Modes Addressing Mode @ERn+/@ERn @(d:16.ERn) @(d:24.ERn) @(d:16.PC) Table A.5 @@aa:8 Functions Instructions @ERn #xx @(d:8.PC) @aa:16 @aa:24 @aa:8 Rn Data MOV transfer POP, PUSH instructions MOVFPE, MOVTPE Arithmetic operations ADD, CMP SUB ADDX, SUBX ADDS, SUBS INC, DEC DAA, DAS MULXU, MULXS, DIVXU, DIVXS NEG EXTU, EXTS Logical AND, OR, XOR operations NOT Shift operations Bit manipulations Branching BCC, BSR instructions JMP, JSR RTS System RTE control SLEEP instructions LDC STC ANDC, ORC, XORC NOP Block data transfer instructions BWL BWL BWL BWL BWL BWL -- -- -- -- -- -- -- -- -- -- -- -- BWL BWL WL BWL B B -- L -- BWL -- -- B BW -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- B -- -- -- -- -- -- -- -- -- BWL BWL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- WL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- B -- B -- -- BWL WL BWL BWL BWL B -- -- -- -- -- B B -- -- -- -- -- -- -- -- B -- -- -- -- W W -- -- -- -- -- -- -- -- -- -- -- -- -- -- W W -- -- -- -- -- -- -- -- -- -- -- -- -- -- W W -- -- -- -- -- -- -- -- -- -- -- -- -- -- W W -- -- -- -- -- -- -- -- B -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- W W -- -- -- -- -- -- -- -- -- -- -- -- -- W W -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BW Rev. 1.00 Dec. 13, 2007 Page 352 of 380 REJ09B0430-0100 -- Appendix B. B.1 I/O Port Block Diagrams Port 3 Block Diagrams SBY PUCR3 VCC VCC PMR3 Internal data bus P3n PDR3 VSS PCR3 AEC module AEVH(P36) AEVL(P37) [Legend] PDR3: PCR3: PMR3: Port data register 3 Port control register 3 Port mode register 3 PUCR3: Port pull-up control register 3 n = 7 or 6 Figure B.1(a) Port 3 Block Diagram (Pins P37 and P36) Rev. 1.00 Dec. 13, 2007 Page 353 of 380 REJ09B0430-0100 Appendix SBY PUCR3 VCC VCC PMR2 Internal data bus P35 PDR3 VSS PCR3 [Legend] PDR3: PCR3: PMR2: Port data register 3 Port control register 3 Port mode register 2 PUCR3: Port pull-up control register 3 Figure B.1(b) Port 3 Block Diagram (Pin P35) Rev. 1.00 Dec. 13, 2007 Page 354 of 380 REJ09B0430-0100 Appendix SBY PUCR3 VCC VCC P3n PDR3 PCR3 VSS [Legend] PUCR3: Port pull-up control register 3 PDR3: PCR3: Port data register 3 Port control register 3 n = 4 or 3 Figure B.1(c) Port 3 Block Diagram (Pins P34 and P33) Rev. 1.00 Dec. 13, 2007 Page 355 of 380 REJ09B0430-0100 Internal data bus Appendix SBY TMOFH (P32) TMOFL (P31) PUCR3 VCC VCC PMR3 P3n PDR3 VSS PCR3 [Legend] PDR3: PCR3: PMR3: Port data register 3 Port control register 3 Port mode register 3 PUCR3: Port pull-up control register 3 n = 2 or 1 Figure B.1(d) Port 3 Block Diagram (Pins P32 and P31) Rev. 1.00 Dec. 13, 2007 Page 356 of 380 REJ09B0430-0100 Internal data bus Appendix B.2 Port 4 Block Diagrams PMR2 P43 Internal data bus IRQ0 [Legend] PMR2: Port mode register 2 Figure B.2(a) Port 4 Block Diagram (Pin P43) Rev. 1.00 Dec. 13, 2007 Page 357 of 380 REJ09B0430-0100 Appendix SBY SCINV3 VCC SPC32 SCI3 module TXD32 Internal data bus P42 PDR4 PCR4 VSS [Legend] PDR4: Port data register 4 PCR4: Port control register 4 Figure B.2(b) Port 4 Block Diagram (Pin P42) Rev. 1.00 Dec. 13, 2007 Page 358 of 380 REJ09B0430-0100 Appendix SBY VCC SCI3 module RE32 RXD32 P41 PDR4 VSS [Legend] PDR4: Port data register 4 PCR4: Port control register 4 SCINV2 Figure B.2(c) Port 4 Block Diagram (Pin P41) Rev. 1.00 Dec. 13, 2007 Page 359 of 380 REJ09B0430-0100 Internal data bus PCR4 Appendix SBY SCI3 module VCC SCKIE32 SCKOE32 SCKO32 SCKI32 P40 PDR4 PCR4 VSS [Legend] PDR4: Port data register 4 PCR4: Port control register 4 Figure B.2(d) Port 4 Block Diagram (Pin P40) Rev. 1.00 Dec. 13, 2007 Page 360 of 380 REJ09B0430-0100 Internal data bus Appendix B.3 Port 5 Block Diagram SBY PUCR5 VCC VCC PMR5 VSS PCR5 Internal data bus P5n PDR5 WKPn [Legend] PDR5: PCR5: PMR5: Port data register 5 Port control register 5 Port mode register 5 PUCR5: Port pull-up control register 5 n = 7 to 0 Figure B.3 Port 5 Block Diagram Rev. 1.00 Dec. 13, 2007 Page 361 of 380 REJ09B0430-0100 Appendix B.4 Port 6 Block Diagram SBY PUCR6 VCC PCR6 P6n VSS [Legend] PDR6: PCR6: Port data register 6 Port control register 6 PUCR6: Port pull-up control register 6 n = 7 to 0 Figure B.4 Port 6 Block Diagram Rev. 1.00 Dec. 13, 2007 Page 362 of 380 REJ09B0430-0100 Internal data bus VCC PDR6 Appendix B.5 Port 7 Block Diagram SBY VCC PDR7 PCR7 P7n VSS [Legend] PDR7: Port data register 7 PCR7: Port control register 7 n = 7 to 0 Figure B.5 Port 7 Block Diagram Rev. 1.00 Dec. 13, 2007 Page 363 of 380 REJ09B0430-0100 Internal data bus Appendix B.6 Port 8 Block Diagram SBY VCC PCR8 P80 VSS [Legend] PDR8: Port data register 8 PCR8: Port control register 8 Figure B.6 Port 8 Block Diagram (Pin P80) Rev. 1.00 Dec. 13, 2007 Page 364 of 380 REJ09B0430-0100 Internal data bus PDR8 Appendix B.7 Port 9 Block Diagrams PWM module PWMn + 1 SBY PMR9 P9n PDR9 VSS [Legend] PMR9: Port mode register 9 PDR9: Port data register 9 n = 1 or 0 Figure B.7(a) Port 9 Block Diagram (Pins P91 and P90) SBY Internal data bus P9n PDR9 VSS [Legend] PDR9: Port data register 9 n = 5 to 2 Figure B.7(b) Port 9 Block Diagram (Pins P95 to P92) Rev. 1.00 Dec. 13, 2007 Page 365 of 380 REJ09B0430-0100 Internal data bus Appendix B.8 Port A Block Diagram SBY VCC PDRA PCRA PAn VSS [Legend] PDRA: Port data register A PCRA: Port control register A n = 3 to 0 Figure B.8 Port A Block Diagram Rev. 1.00 Dec. 13, 2007 Page 366 of 380 REJ09B0430-0100 Internal data bus Appendix B.9 Port B Block Diagrams PBn Internal data bus A/D module DEC AMR3 to AMR0 VIN n = 3 to 0 Figure B.9 Port B Block Diagram Rev. 1.00 Dec. 13, 2007 Page 367 of 380 REJ09B0430-0100 Appendix C. Port States in Each Operating State Port States Reset Sleep Subsleep Retained Retained Retained Retained Retained Retained Retained Retained Standby Watch Subactive Active Functioning Functioning Functioning Functioning Functioning Functioning Functioning Functioning Functioning Functioning Functioning Functioning Functioning Functioning Functioning Functioning Table C.1 Port P37 to P31 High Retained impedance P43 to P40 High Retained impedance P57 to P50 High Retained impedance P67 to P60 High Retained impedance P77 to P70 High Retained impedance P80 High Retained impedance High Retained impedance* High impedance Retained High Retained impedance* High Retained impedance* High impedance High impedance High impedance High impedance Retained Retained Retained Retained P95 to P90 High Retained impedance PA3 to PA0 High Retained impedance PB3 to PB0 High High High High impedance impedance impedance impedance Note: * High High High impedance impedance impedance High level output when the pull-up MOS is in on state. Rev. 1.00 Dec. 13, 2007 Page 368 of 380 REJ09B0430-0100 Appendix D. Product Code Lineup Product Code Lineup of H8/38704 Group Product Code Regular product (2.7 V) Regular product (2.2 V) Product with wide-range temperature specifications (2.7 V) Mask ROM version Regular product HD64F38704H10 HD64F38704FP10 HD64F38704FT10 HD64F38704H4 HD64F38704FP4 HD64F38704 FT4 HD64F38704H10W HD64F38704FP10W HD64F38704FT10W Model Marking 64F38704H10 F38704FP10 F38704FT10 64F38704H4 F38704FP4 F38704FT4 64F38704H10 F38704FP10 38704FT10 Package (Package Code) 64-pin QFP (FP-64A) 64-pin LQFP (FP-64E) 64-pin QFN (TNP-64B) 64-pin QFP (FP-64A) 64-pin LQFP (FP-64E) 64-pin QFN (TNP-64B) 64-pin QFP (FP-64A) 64-pin LQFP (FP-64E) 64-pin QFN (TNP-64B) Table D.1 Product Type H8/38704 Flash memory version HD64338704H HD64338704FP HD64338704FT HD64338704H 38704 (***) FP 38704 (***) FT HD64338704H 38704 (***) FP 38704 (***) FT HD64338703H 38703 (***) FP 38703 (***) FT HD64338703H 38703 (***) FP 38703 (***) FT 64-pin QFP (FP-64A) 64-pin LQFP (FP-64E) 64-pin QFN (TNP-64B) 64-pin QFP (FP-64A) 64-pin LQFP (FP-64E) 64-pin QFN (TNP-64B) 64-pin QFP (FP-64A) 64-pin LQFP (FP-64E) 64-pin QFN (TNP-64B) 64-pin QFP (FP-64A) 64-pin LQFP (FP-64E) 64-pin QFN (TNP-64B) Product with wide-range temperature specifications H8/38703 Mask ROM version Regular product HD64338704HW HD64338704FPW HD64338704FTW HD64338703H HD64338703FP HD64338703FT Product with wide-range temperature specifications HD64338703HW HD64338703FPW HD64338703FTW Rev. 1.00 Dec. 13, 2007 Page 369 of 380 REJ09B0430-0100 Appendix Product Type H8/38702 Product Code Flash memory version Package Model Marking (Package Code) Regular product (2.7 V) Regular product (2.2 V) Product with wide-range temperature specifications (2.7 V) HD64F38702H10 HD64F38702FP10 HD64F38702FT10 HD64F38702H4 HD64F38702FP4 HD64F38702FT4 HD64F38702H10W HD64F38702FP10W HD64F38702FT10W Product Type 64F38702H10 F38702FP10 F38702FT10 64F38702H4 F38702FP4 F38702FT4 64F38702H10 F38702FP10 F38702FT10 Product Code 64-pin QFP (FP-64A) 64-pin LQFP (FP-64E) 64-pin QFN (TNP-64B) 64-pin QFP (FP-64A) 64-pin LQFP (FP-64E) 64-pin QFN (TNP-64B) 64-pin QFP (FP-64A) 64-pin LQFP (FP-64E) 64-pin QFN (TNP-64B) Mask ROM version Regular product HD64338702H HD64338702FP HD64338702FT HD64338702H 38702 (***) FP 38702 (***) FT HD64338702H 38702 (***) FP 38702 (***) FT 64-pin QFP (FP-64A) 64-pin LQFP (FP-64E) 64-pin LQFN (TNP-64B) 64-pin QFP (FP-64A) 64-pin LQFP (FP-64E) 64-pin QFN (TNP-64B) Product with wide-range temperature specifications HD64338702HW HD64338702FPW HD64338702FTW [Legend] (***): ROM code Rev. 1.00 Dec. 13, 2007 Page 370 of 380 REJ09B0430-0100 Appendix Table D.2 Product Type H8/38702S Product Code Lineup of H8/38702S Group Product Code Regular product HD64338702SH HD64338702SFZ HD64338702SFT Product with wide-range temperature specifications HD64338702SHW Model Marking 38702 (***) H 38702 (***) 38702 (***) FT 38702 (***) H Package (Package Code) 64-pin QFP (FP-64A) 64-pin LQFP (FP-64K) 64-pin QFN (TNP-64B) 64-pin QFP (FP-64A) 64-pin LQFP (FP-64K) 64-pin QFN (TNP-64B) 64-pin QFP (FP-64A) 64-pin LQFP (FP-64K) 64-pin QFN (TNP-64B) 64-pin QFP (FP-64A) 64-pin LQFP (FP-64K) 64-pin QFN (TNP-64B) 64-pin QFP (FP-64A) 64-pin LQFP (FP-64K) 64-pin QFN (TNP-64B) 64-pin QFP (FP-64A) 64-pin LQFP (FP-64K) 64-pin QFN (TNP-64B) Mask ROM version HD64338702SFZW 38702 (***) HD64338702SFTW 38702 (***) FT HD64338701SH HD64338701SFZ HD64338701SFT 38701 (***) H 38701 (***) 38701 (***) FT 38701 (***) H H8/38701S Mask ROM version Regular product Product with wide-range temperature specifications H8/38700S Mask ROM version Regular product HD64338701SHW HD64338701SFZW 38701 (***) HD64338701SFTW 38701 (***) FT HD64338700SH HD64338700SFZ HD64338700SFT 38700 (***) H 38700 (***) 38700 (***) FT 38700 (***) H Product with wide-range temperature specifications HD64338700SHW HD64338700SFZW 38700 (***) HD64338700SFTW 38700 (***) FT [Legend] (***): ROM code Rev. 1.00 Dec. 13, 2007 Page 371 of 380 REJ09B0430-0100 Appendix E. Package Dimensions The package dimensions are shown in figure E.1 (FP-64A), figure E.2 (FP-64E), figure E.3 (FP64K), and figure E.4 (TNP-64B). JEITA Package Code P-QFP64-14x14-0.80 RENESAS Code PRQP0064GB-A Previous Code FP-64A/FP-64AV MASS[Typ.] 1.2g HD *1 D 33 48 NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. 49 32 bp b1 Reference Symbol Dimension in Millimeters Min Nom 14 14 2.70 16.9 16.9 17.2 17.2 17.5 17.5 3.05 0.00 0.29 0.10 0.37 0.35 0.12 0.17 0.15 0 0.8 0.15 0.10 1.0 1.0 0.5 0.8 1.6 1.1 8 0.22 0.25 0.45 Max c1 HE E c D E A2 *2 Terminal cross section ZE HD HE A A1 bp 17 64 1 ZD 16 A2 b1 c F c1 A c A1 e x y ZD ZE L L1 L L1 Detail F e *3 y bp x M Figure E.1 Package Dimensions (FP-64A) Rev. 1.00 Dec. 13, 2007 Page 372 of 380 REJ09B0430-0100 Appendix JEITA Package Code P-LQFP64-10x10-0.50 RENESAS Code PLQP0064KC-A Previous Code FP-64E/FP-64EV MASS[Typ.] 0.4g HD *1 D 33 NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. 48 49 32 bp b1 Reference Symbol Dimension in Millimeters Min Nom 10 10 1.45 11.8 11.8 12.0 12.0 12.2 12.2 1.70 0.00 0.17 0.10 0.22 0.20 0.12 0.17 0.15 0 0.5 0.08 0.10 1.25 1.25 0.3 0.5 1.0 0.7 8 0.22 0.20 0.27 Max c1 HE E c D E A2 *2 Terminal cross section 64 17 HD HE A A1 ZE 1 ZD Index mark 16 bp b1 c A2 A c F c1 e x y ZD ZE L L1 A1 L L1 e *3 Detail F bp x M y Figure E.2 Package Dimensions (FP-64E) Rev. 1.00 Dec. 13, 2007 Page 373 of 380 REJ09B0430-0100 Appendix JEITA Package Code P-LQFP64-10x10-0.50 RENESAS Code PLQP0064KB-A Previous Code 64P6Q-A / FP-64K / FP-64KV MASS[Typ.] 0.3g HD *1 48 D 33 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. bp b1 49 32 HE E Reference Symbol *2 c1 Dimension in Millimeters Min 9.9 9.9 Nom 10.0 10.0 1.4 11.8 11.8 12.0 12.0 12.2 12.2 1.7 0.05 0.15 0.1 0.20 0.18 0.09 0.145 0.125 0 8 0.5 0.08 0.08 1.25 1.25 0.35 0.5 1.0 0.65 0.20 0.15 0.25 Max 10.1 10.1 c D 64 E ZE 17 Terminal cross section A2 HD 1 Index mark ZD 1 6 HE A A1 F bp b1 A2 A c c1 A1 y e *3 bp x c L L1 Detail F e x y ZD ZE L L1 Figure E.3 Package Dimensions (FP-64K) Rev. 1.00 Dec. 13, 2007 Page 374 of 380 REJ09B0430-0100 Appendix JEITA Package Code P-VQFN64-8x8-0.40 RENESAS Code PVQN0064LB-A Previous Code TNP-64B/TNP-64BV MASS[Typ.] 0.12g HD D 48 33 49 32 HE E e Reference Symbol Dimension in Millimeters Min 64 17 1 x4 t 16 ZD b b1 xn A2 y1 y D E A2 A A1 b b1 e Lp x y y1 t HD HE ZD ZE c c1 Nom 8.0 8.0 0.89 0.02 0.18 0.16 0.4 0.60 Max ZE Lp 0.005 0.13 0.95 0.04 0.23 0.50 0.70 0.05 0.05 0.2 0.2 c c1 A1 A 0.17 8.2 8.2 1.0 1.0 0.22 0.20 0.25 Figure E.4 Package Dimensions (TNP-64B) Rev. 1.00 Dec. 13, 2007 Page 375 of 380 REJ09B0430-0100 Appendix Rev. 1.00 Dec. 13, 2007 Page 376 of 380 REJ09B0430-0100 Index Numerics 10-bit PWM ............................................ 267 16-bit timer mode ................................... 191 8-bit timer mode ..................................... 191 E Effective address....................................... 43 Effective address extension....................... 38 Erase/erase-verify ................................... 125 Erasing units ........................................... 112 Error protection....................................... 127 Exception handling ................................... 55 A A/D converter ......................................... 273 Absolute address....................................... 40 Addressing modes..................................... 39 Arithmetic operations instructions............ 30 Asynchronous mode ............................... 238 Auto-erase mode..................................... 136 Auto-program mode................................ 134 F Flash memory ......................................... 110 Framing error .......................................... 246 G General registers ....................................... 22 B Bit manipulation instructions.................... 33 Bit rate .................................................... 231 Block data transfer instructions ................ 37 Boot mode .............................................. 117 Boot program.......................................... 117 Branch instructions ................................... 35 Break....................................................... 261 H Hardware protection................................ 127 I Immediate ................................................. 41 Instruction set............................................ 28 Internal interrupts...................................... 67 Interrupt mask bit (I)................................. 23 Interrupt response time ............................. 69 IRQ interrupts ........................................... 66 C Clock pulse generators.............................. 75 Clocked synchronous mode .................... 250 Condition field.......................................... 38 Condition-code register (CCR)................. 23 CPU .......................................................... 13 L Large current ports...................................... 4 Logic operations instructions .................... 32 D Data transfer instructions.......................... 29 Rev. 1.00 Dec. 13, 2007 Page 377 of 380 REJ09B0430-0100 M Mark state ............................................... 261 Memory indirect ....................................... 41 Memory map ............................................ 15 Memory read mode................................. 131 Module standby function ........................ 106 O On-board programming modes............... 117 Operation field.......................................... 38 Overrun error .......................................... 246 P Parity error.............................................. 246 Pin assignment............................................ 8 Power-down modes .................................. 87 Power-down state ................................... 141 Prescaler S ................................................ 80 Prescaler W............................................... 80 Program counter (PC)............................... 23 Program/program-verify......................... 122 Program-counter relative .......................... 41 Programmer mode .................................. 128 Programming units ................................. 112 R Register ADRR..........................275, 287, 290, 293 ADSR ..........................277, 287, 290, 293 AEGSR........................203, 286, 289, 292 AMR............................276, 287, 290, 293 BRR .............................231, 286, 289, 292 CKSTPR1 ......................91, 288, 291, 294 CKSTPR2 ......................91, 288, 291, 294 EBR .............................115, 286, 289, 292 ECCR...........................204, 286, 289, 292 ECCSR ........................205, 286, 289, 292 Rev. 1.00 Dec. 13, 2007 Page 378 of 380 REJ09B0430-0100 ECPWCR.................... 201, 286, 289, 292 ECPWDR.................... 202, 286, 289, 292 FENR .......................... 116, 286, 289, 292 FLMCR1..................... 114, 286, 289, 292 FLMCR2..................... 115, 286, 289, 292 FLPWCR .................... 116, 286, 289, 292 IEGR ............................. 59, 288, 291, 294 IENR ............................. 60, 288, 291, 294 IRR................................ 62, 288, 291, 294 IWPR ............................ 64, 288, 291, 294 OCR ............................ 185, 287, 290, 293 PCR3........................... 148, 288, 290, 293 PCR4........................... 155, 288, 290, 293 PCR5........................... 159, 288, 291, 294 PCR6........................... 163, 288, 291, 294 PCR7........................... 166, 288, 291, 294 PCR8........................... 168, 288, 291, 294 PCRA.......................... 172, 288, 291, 294 PDR3........................... 148, 287, 290, 293 PDR4........................... 154, 287, 290, 293 PDR5........................... 159, 287, 290, 293 PDR6........................... 163, 287, 290, 293 PDR7........................... 166, 287, 290, 293 PDR8........................... 168, 287, 290, 293 PDR9........................... 169, 287, 290, 293 PDRA.......................... 171, 287, 290, 293 PDRB.......................... 174, 288, 290, 293 PMR2.......................... 151, 287, 290, 293 PMR3.......................... 150, 287, 290, 293 PMR5.......................... 160, 287, 290, 293 PMR9.......................... 170, 288, 291, 294 PMRB ......................... 174, 288, 291, 294 PUCR3........................ 149, 288, 290, 293 PUCR5........................ 160, 288, 290, 293 PUCR6........................ 164, 288, 290, 293 PWCR ......................... 269, 287, 290, 293 PWDR......................... 270, 287, 290, 293 RDR ............................ 222, 286, 289, 292 RSR..................................................... 221 SCR3........................... 226, 286, 289, 292 SMR............................ 223, 286, 289, 292 SPCR .......................... 155, 286, 289, 292 SSR ............................. 228, 286, 289, 292 SYSCR1 ....................... 88, 288, 291, 294 SYSCR2 ....................... 90, 288, 291, 294 TCA ............................ 181, 287, 289, 292 TCR ............................ 186, 287, 290, 293 TCSR .......................... 187, 287, 290, 293 TCSRW ...................... 215, 287, 289, 292 TCW ........................... 216, 287, 289, 292 TDR ............................ 222, 286, 289, 292 TMA ........................... 180, 287, 289, 292 TSR..................................................... 222 WEGR .......................... 65, 286, 289, 292 Register direct........................................... 39 Register field............................................. 38 Register indirect........................................ 40 Register indirect with displacement.......... 40 Register indirect with post-increment....... 40 Register indirect with pre-decrement........ 40 Reset exception handling.......................... 65 Socket adapter......................................... 128 Software protection................................. 127 Stack pointer (SP) ..................................... 22 Stack status ............................................... 69 Standby mode ........................................... 99 Status polling .......................................... 139 Status read mode ..................................... 137 Subactive mode....................................... 100 Subclock generator.................................... 78 Subsleep mode ........................................ 100 System clock generator ............................. 76 System control instructions....................... 36 T Timer A................................................... 178 Timer F ................................................... 182 V Vector address........................................... 58 S Serial communication interface 3 (SCI3) ..................................................... 219 Shift instructions....................................... 32 Sleep mode ............................................... 98 W Watchdog timer....................................... 214 WKP interrupts ......................................... 66 Rev. 1.00 Dec. 13, 2007 Page 379 of 380 REJ09B0430-0100 Rev. 1.00 Dec. 13, 2007 Page 380 of 380 REJ09B0430-0100 Renesas 16-Bit Single-Chip Microcomputer Hardware Manual H8/38704 Group, H8/38702S Group Publication Date: Rev.1.00, Dec. 13, 2007 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp. 2007. Renesas Technology Corp., All rights reserved. Printed in Japan. Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120 Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7858/7898 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2377-3473 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 3518-3399 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145 http://www.renesas.com Renesas Technology Malaysia Sdn. Bhd Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: <603> 7955-9390, Fax: <603> 7955-9510 Colophon 6.2 H8/38704 Group, H8/38702S Group Hardware Manual |
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